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Features
* High-performance, Low-power 8/16-bit AVR XMEGA Microcontroller * Non-volatile Program and Data Memories
- 64 KB - 256 KB of In-System Self-Programmable Flash - 4 KB - 8 KB Boot Code Section with Independent Lock Bits - 2 KB - 4 KB EEPROM - 4 KB - 16 KB Internal SRAM Peripheral Features - Four-channel DMA Controller with support for external requests - Eight-channel Event System - Seven 16-bit Timer/Counters Four Timer/Counters with 4 Output Compare or Input Capture channels Three Timer/Counters with 2 Output Compare or Input Capture channels High Resolution Extensions on all Timer/Counters Advanced Waveform Extension on one Timer/Counter - Seven USARTs IrDA Extension on 1 USART - AES and DES Crypto Engine - Two Two-wire Interfaces with dual address match (I2C and SMBus compatible) - Three SPI (Serial Peripheral Interfaces) - 16-bit Real Time Counter with Separate Oscillator - Two Eight-channel, 12-bit, 2 Msps Analog to Digital Converters - One Two-channel, 12-bit, 1 Msps Digital to Analog Converter - Four Analog Comparators with Window compare function - External Interrupts on all General Purpose I/O pins - Programmable Watchdog Timer with Separate On-chip Ultra Low Power Oscillator Special Microcontroller Features - Power-on Reset and Programmable Brown-out Detection - Internal and External Clock Options with PLL - Programmable Multi-level Interrupt Controller - Sleep Modes: Idle, Power-down, Standby, Power-save, Extended Standby - Advanced Programming, Test and Debugging Interfaces JTAG (IEEE 1149.1 Compliant) Interface for test, debug and programming PDI (Program and Debug Interface) for programming, test and debugging I/O and Packages - 50 Programmable I/O Lines - 64-lead TQFP - 64-pad QFN Operating Voltage - 1.6 - 3.6V Speed performance - 0 - 12 MHz @ 1.6 - 3.6V - 0 - 32 MHz @ 2.7 - 3.6V
*
8/16-bit XMEGA A3 Microcontroller
ATxmega256A3 ATxmega192A3 ATxmega128A3 ATxmega64A3
Preliminary
*
*
* *
Typical Applications
* * * * *
Industrial control Factory automation Building control Board control White Goods
* * * * *
Climate control ZigBee Motor control Networking Optical
* * * * *
Hand-held battery applications Power tools HVAC Metering Medical Applications
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1. Ordering Information
Ordering Code ATxmega256A3-AU ATxmega192A3-AU ATxmega128A3-AU ATxmega64A3-AU ATxmega256A3-MH ATXMEGA192A3-MH ATxmega128A3-MH ATxmega64A3-MH
Notes: 1. 2. 3.
Flash 256 KB + 8 KB 192 KB + 8 KB 128 KB + 8 KB 64 KB + 4 KB 256 KB + 8 KB 192 KB + 8 KB 128 KB + 8 KB 64 KB + 4 KB
E2 4 KB 4 KB 2 KB 2 KB 4 KB 4 KB 2 KB 2 KB
SRAM 16 KB 16 KB 8 KB 4 KB 16 KB 16 KB 8 KB 4 KB
Speed (MHz) 32 32 32 32 32 32 32 32
Power Supply 1.6 - 3.6V 1.6 - 3.6V 1.6 - 3.6V 1.6 - 3.6V 1.6 - 3.6V 1.6 - 3.6V 1.6 - 3.6V 1.6 - 3.6V
Package(1)(2)(3)
Temp
64A
-40C - 85C
64M2
This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully Green. For packaging information, see "Errata" on page 90
Package Type 64A 64M2
64-lead, 14 x 14 mm Body Size, 1.0 mm Body Thickness, 0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP) 64-Pad, 9 x 9 x 1.0 mm Body, Lead Pitch 0.50 mm, 7.65 mm Exposed Pad, Quad Flat No-Lead Package (QFN)
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2. Pinout/Block Diagram
Figure 2-1. Block diagram and pinout.
PA2 PA1 PA0 AVCC GND PR1 PR0 RESET/PDI_CLK PDI_DATA PF7 PF6 VCC GND PF5 PF4 PF3 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
INDEX CORNER
PA3 PA4 PA5 PA6 PA7 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 GND VCC PC0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Port R
DATA BU S
ADC A
OSC/CLK Control
Port A
BOD TEMP
VREF RTC
POR OCD
AC A0 Power Control
AC A1 ADC B
FLASH CPU RAM
E2PROM
Port B
DAC B AC B0
Reset Control
DMA
Interrupt Controller Watchdog Event System ctrl
DATA BU S EVENT ROUTING NETWORK
AC B1
Port C
Port D
Port E
Port F
PF2 PF1 PF0 VCC GND PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 VCC GND PD7
USART0:1
USART0:1
USART0:1
T/C0:1
Note:
1. For full details on pinout and alternate pin functions refer to "Pinout and Pin Functions" on page 49.
PC1 PC2 PC3 PC4 PC5 PC6 PC7 GND VCC PD0 PD1 PD2 PD3 PD4 PD5 PD6
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
SPI
USART0
T/C0:1
T/C0:1
T/C0
TWI
TWI
SPI
SPI
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3. Overview
The XMEGA A3 is a family of low power, high performance and peripheral rich CMOS 8/16-bit microcontrollers based on the AVR (R) enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the XMEGA A3 achieves throughputs approaching 1 Million Instructions Per Second (MIPS) per MHz allowing the system designer to optimize power consumption versus processing speed. The AVR CPU combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction, executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs many times faster than conventional single-accumulator or CISC based microcontrollers. The XMEGA A3 devices provide the following features: In-System Programmable Flash with Read-While-Write capabilities, Internal EEPROM and SRAM, four-channel DMA Controller, eight-channel Event System, Programmable Multi-level Interrupt Controller, 50 general purpose I/O lines, 16-bit Real Time Counter (RTC), seven flexible 16-bit Timer/Counters with compare modes and PWM, seven USARTs, two Two Wire Serial Interfaces (TWIs), three Serial Peripheral Interfaces (SPIs), AES and DES crypto engine, two 8-channel 12-bit ADCs with optional differential input with programmable gain, one 2-channel 12-bit DACs, four analog comparators with window mode, programmable Watchdog Timer with separate Internal Oscillator, accurate internal oscillators with PLL and prescaler and programmable Brown-Out Detection. The Program and Debug Interface (PDI), a fast 2-pin interface for programming and debugging, is available. The devices also have an IEEE std. 1149.1 compliant JTAG test interface, and this can also be used for On-chip Debug and programming. The XMEGA A3 devices have five software selectable power saving modes. The Idle mode stops the CPU while allowing the SRAM, DMA Controller, Event System, Interrupt Controller and all peripherals to continue functioning. The Power-down mode saves the SRAM and register contents but stops the oscillators, disabling all other functions until the next TWI or pin-change interrupt, or Reset. In Power-save mode, the asynchronous Real Time Counter continues to run, allowing the application to maintain a timer base while the rest of the device is sleeping. In Standby mode, the Crystal/Resonator Oscillator is kept running while the rest of the device is sleeping. This allows very fast start-up from external crystal combined with low power consumption. In Extended Standby mode, both the main Oscillator and the Asynchronous Timer continue to run. To further reduce power consumption, the peripheral clock for each individual peripheral can optionally be stopped in Active mode and Idle sleep mode. The device is manufactured using Atmel's high-density nonvolatile memory technology. The program Flash memory can be reprogrammed in-system through the PDI or JTAG. A Bootloader running in the device can use any interface to download the application program to the Flash memory. The Bootloader software in the Boot Flash section will continue to run while the Application Flash section is updated, providing true Read-While-Write operation. By combining an 8/16-bit RISC CPU with In-System Self-Programmable Flash, the Atmel XMEGA A3 is a powerful microcontroller family that provides a highly flexible and cost effective solution for many embedded applications. The XMEGA A3 devices are supported with a full suite of program and system development tools including: C compilers, macro assemblers, program debugger/simulators, programmers, and evaluation kits.
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3.1 Block Diagram
XMEGA A3 Block Diagram
PR[0..1] XTAL1
Figure 3-1.
XTAL2
PORT R (2)
Oscillator Circuits/ Clock Generation
Watchdog Oscillator Real Time Counter Watchdog Timer
DATA BUS PA[0..7] PORT A (8) Event System Controller ACA ADCA DMA Controller SRAM Sleep Controller PDI AREFA VCC/10 Int. Ref. Tempref AREFB AES ADCB ACB USARTF0 TCF0 Flash DACB EEPROM PB[0..7]/ JTAG PORT F (8) NVM Controller PORT B (8) DES CPU Interrupt Controller OCD PDI_DATA BUS Controller Prog/Debug Controller JTAG PORT B Oscillator Control Power Supervision POR/BOD & RESET VCC
GND RESET/ PDI_CLK
PF[0..7]
IRCOM
DATA BUS
EVENT ROUTING NETWORK
USARTC0:1
USARTD0:1
USARTE0:1
TCC0:1
TCD0:1
TCE0:1
TWIC
TWIE
SPIC
SPID
SPIE
To Clock Generator PORT C (8) PORT D (8) PORT E (8)
TOSC1
TOSC2 PC[0..7] PD[0..7] PE[0..7]
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4. Resources
A comprehensive set of development tools, application notes and datasheets are available for download on http://www.atmel.com/avr.
4.1
Recommended reading
* XMEGA Manual * XMEGA Application Notes This device data sheet only contains part specific information and a short description of each peripheral and module. The XMEGA Manual describes the modules and peripherals in depth. The XMEGA application notes contain example code and show applied use of the modules and peripherals. The XMEGA Manual and Application Notes are available from http://www.atmel.com/avr.
5. Disclaimer
For devices that are not available yet, typical values contained in this datasheet are based on simulations and characterization of other AVR XMEGA microcontrollers manufactured on the same process technology. Min. and Max values will be available after the device is characterized.
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6. AVR CPU
6.1 Features
* 8/16-bit high performance AVR RISC Architecture
- 138 instructions - Hardware multiplier 32x8-bit registers directly connected to the ALU Stack in RAM Stack Pointer accessible in I/O memory space Direct addressing of up to 16M bytes of program and data memory True 16/24-bit access to 16/24-bit I/O registers Support for 8-, 16- and 32-bit Arithmetic Configuration Change Protection of system critical features
* * * * * * *
6.2
Overview
The XMEGA A3 uses an 8/16-bit AVR CPU. The main function of the AVR CPU is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations and control peripherals. Interrupt handling is described in a separate section. Figure 6-1 on page 7 shows the CPU block diagram. Figure 6-1. CPU block diagram
DATA BUS
Program Counter
Flash Program Memory 32 x 8 General Purpose Registers
OCD
Instruction Register
STATUS/ CONTROL
Instruction Decode
ALU
Multiplier/ DES
DATA BUS
Peripheral Module 1
Peripheral Module 2
SRAM
EEPROM
PMIC
The AVR uses a Harvard architecture - with separate memories and buses for program and data. Instructions in the program memory are executed with a single level pipeline. While one instruction is being executed, the next instruction is pre-fetched from the program memory.
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This concept enables instructions to be executed in every clock cycle. The program memory is In-System Re-programmable Flash memory.
6.3
Register File
The fast-access Register File contains 32 x 8-bit general purpose working registers with a single clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typical ALU operation, two operands are output from the Register File, the operation is executed, and the result is stored back in the Register File - in one clock cycle. Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space addressing - enabling efficient address calculations. One of these address pointers can also be used as an address pointer for look up tables in Flash program memory.
6.4
ALU - Arithmetic Logic Unit
The high performance Arithmetic Logic Unit (ALU) supports arithmetic and logic operations between registers or between a constant and a register. Single register operations can also be executed. Within a single clock cycle, arithmetic operations between general purpose registers or between a register and an immediate are executed. After an arithmetic or logic operation, the Status Register is updated to reflect information about the result of the operation. The ALU operations are divided into three main categories - arithmetic, logical, and bit-functions. Both 8- and 16-bit arithmetic is supported, and the instruction set allows for easy implementation of 32-bit arithmetic. The ALU also provides a powerful multiplier supporting both signed and unsigned multiplication and fractional format.
6.5
Program Flow
When the device is powered on, the CPU starts to execute instructions from the lowest address in the Flash Program Memory `0'. The Program Counter (PC) addresses the next instruction to be fetched. After a reset, the PC is set to location `0'. Program flow is provided by conditional and unconditional jump and call instructions, capable of addressing the whole address space directly. Most AVR instructions use a 16-bit word format, while a limited number uses a 32-bit format. During interrupts and subroutine calls, the return address PC is stored on the Stack. The Stack is effectively allocated in the general data SRAM, and consequently the Stack size is only limited by the total SRAM size and the usage of the SRAM. After reset the Stack Pointer (SP) points to the highest address in the internal SRAM. The SP is read/write accessible in the I/O memory space, enabling easy implementation of multiple stacks or stack areas. The data SRAM can easily be accessed through the five different addressing modes supported in the AVR CPU.
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7. Memories
7.1 Features
* Flash Program Memory
- One linear address space - In-System Programmable - Self-Programming and Bootloader support - Application Section for application code - Application Table Section for application code or data storage - Boot Section for application code or bootloader code - Separate lock bits and protection for all sections - Built in fast CRC check of a selectable flash program memory section * Data Memory - One linear address space - Single cycle access from CPU - SRAM - EEPROM Byte and page accessible Optional memory mapping for direct load and store - I/O Memory Configuration and Status registers for all peripherals and modules 16 bit-accessible General Purpose Register for global variables or flags - Bus arbitration Safe and deterministic handling of CPU and DMA Controller priority - Separate buses for SRAM, EEPROM, I/O Memory and External Memory access Simultaneous bus access for CPU and DMA Controller * Production Signature Row Memory for factory programmed data Device ID for each microcontroller device type Serial number for each device Oscillator calibration bytes ADC, DAC and temperature sensor calibration data * User Signature Row One flash page in size Can be read and written from software Content is kept after chip erase
7.2
Overview
The AVR architecture has two main memory spaces, the Program Memory and the Data Memory. In addition, the XMEGA A3 features an EEPROM Memory for non-volatile data storage. All three memory spaces are linear and require no paging. The available memory size configurations are shown in "Ordering Information" on page 2. In addition each device has a Flash memory signature row for calibration data, device identification, serial number etc. Non-volatile memory spaces can be locked for further write or read/write operations. This prevents unrestricted access to the application software.
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7.3 In-System Programmable Flash Program Memory
The XMEGA A3 devices contains On-chip In-System Programmable Flash memory for program storage, see Figure 7-1 on page 10. Since all AVR instructions are 16- or 32-bits wide, each Flash address location is 16 bits. The Program Flash memory space is divided into Application and Boot sections. Both sections have dedicated Lock Bits for setting restrictions on write or read/write operations. The Store Program Memory (SPM) instruction must reside in the Boot Section when used to write to the Flash memory. A third section inside the Application section is referred to as the Application Table section which has separate Lock bits for storage of write or read/write protection. The Application Table section can be used for storing non-volatile data or application software.
Figure 7-1.
Flash Program Memory (Hexadecimal address)
Word Address 0 Application Section (256 KB/192 KB/128 KB/64 KB) ... 1EFFF 1F000 1FFFF 20000 20FFF / / / / / 16FFF 17000 17FFF 18000 18FFF / / / / / EFFF F000 FFFF 10000 10FFF / / / / / 77FF 7800 7FFF 8000 87FF Application Table Section (8 KB/8 KB/8 KB/4 KB) Boot Section (8 KB/8 KB/8 KB/4 KB)
The Application Table Section and Boot Section can also be used for general application software.
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7.4 Data Memory
The Data Memory consist of the I/O Memory, EEPROM and SRAM memories, all within one linear address space, see Figure 7-2 on page 11. To simplify development, the memory map for all devices in the family is identical and with empty, reserved memory space for smaller devices.
Figure 7-2.
Data Memory Map (Hexadecimal address)
ATxmega192A3 I/O Registers (4 KB) EEPROM (4 KB) Byte Address 0 FFF 1000 17FF ATxmega128A3 I/O Registers (4 KB) EEPROM (2 KB)
RESERVED
Byte Address 0 FFF 1000
Byte Address 0 FFF 1000 17FF
ATxmega64A3 I/O Registers (4 KB) EEPROM (2 KB)
RESERVED
1FFF 2000 5FFF Internal SRAM (16 KB) 2000 3FFF
Internal SRAM (8 KB)
2000 2FFF
Internal SRAM (4 KB)
Byte Address 0 FFF 1000
ATxmega256A3 I/O Registers (4 KB) EEPROM (4 KB)
1FFF 2000 5FFF Internal SRAM (16 KB)
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7.4.1 I/O Memory All peripherals and modules are addressable through I/O memory locations in the data memory space. All I/O memory locations can be accessed by the Load (LD/LDS/LDD) and Store (ST/STS/STD) instructions, transferring data between the 32 general purpose registers in the CPU and the I/O Memory. The IN and OUT instructions can address I/O memory locations in the range 0x00 - 0x3F directly. I/O registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. The value of single bits can be checked by using the SBIS and SBIC instructions on these registers. The I/O memory address for all peripherals and modules in XMEGA A3 is shown in the "Peripheral Module Address Map" on page 54. 7.4.2 SRAM Data Memory The XMEGA A3 devices have internal SRAM memory for data storage. 7.4.3 EEPROM Data Memory The XMEGA A3 devices have internal EEPROM memory for non-volatile data storage. It is addressable either in a separate data space or it can be memory mapped into the normal data memory space. The EEPROM memory supports both byte and page access.
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7.5 Production Signature Row
The Production Signature Row is a separate memory section for factory programmed data. It contains calibration data for functions such as oscillators and analog modules. The production signature row also contains a device ID that identify each microcontroller device type, and a serial number that is unique for each manufactured device. The device ID for the available XMEGA A3 devices is shown in Table 7-1 on page 13. The serial number consist of the production LOT number, wafer number, and wafer coordinates for the device. The production signature row can not be written or erased, but it can be read from both application software and external programming. Table 7-1. Device ID bytes for XMEGA A3 devices.
Device Byte 2 ATxmega64A3 ATxmega128A3 ATxmega192A3 ATxmega256A3 42 42 44 42 Device ID bytes Byte 1 96 97 97 98 Byte 0 1E 1E 1E 1E
7.6
User Signature Row
The User Signature Row is a separate memory section that is fully accessible (read and write) from application software and external programming. The user signature row is one flash page in size, and is meant for static user parameter storage, such as calibration data, custom serial numbers or identification numbers, random number seeds etc. This section is not erased by Chip Erase commands that erase the Flash, and requires a dedicated erase command. This ensures parameter storage during multiple program/erase session and on-chip debug sessions.
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7.7 Flash and EEPROM Page Size
The Flash Program Memory and EEPROM data memory are organized in pages. The pages are word accessible for the Flash and byte accessible for the EEPROM. Table 7-2 on page 14 shows the Flash Program Memory organization. Flash write and erase operations are performed on one page at a time, while reading the Flash is done one byte at a time. For Flash access the Z-pointer (Z[m:n]) is used for addressing. The most significant bits in the address (FPAGE) gives the page number and the least significant address bits (FWORD) gives the word in the page.
Table 7-2.
Devices Flash Size ATxmega64A3 ATxmega128A3 ATxmega192A3 ATxmega256A3 64 KB + 4 KB 128 KB + 8 KB 192 KB + 8 KB 256 KB + 8 KB Page Size (words) 128 256 256 256
Number of words and Pages in the Flash.
FWORD FPAGE Application Size Z[7:1] Z[8:1] Z[8:1] Z[8:1] Z[16:8] Z[17:9] Z[18:9] Z[18:9] 64K 128K 192K 256K No of Pages 256 256 384 512 Size 4 KB 8 KB 8 KB 8 KB Boot No of Pages 16 16 16 16
Table 7-3 on page 14 shows EEPROM memory organization for the XMEGA A3 devices. EEEPROM write and erase operations can be performed one page or one byte at a time, while reading the EEPROM is done one byte at a time. For EEPROM access the NVM Address Register (ADDR[m:n]) is used for addressing. The most significant bits in the address (E2PAGE) gives the page number and the least significant address bits (E2BYTE) gives the byte in the page.
Table 7-3.
Devices EEPROM Size ATxmega64A3 ATxmega128A3 ATxmega192A3 ATxmega256A3 2 KB 2 KB 2 KB 4 KB
Number of bytes and Pages in the EEPROM.
Page Size (Bytes) 32 32 32 32 ADDR[4:0] ADDR[4:0] ADDR[4:0] ADDR[4:0] ADDR[10:5] ADDR[10:5] ADDR[10:5] ADDR[11:5] 64 64 64 128 E2BYTE E2PAGE No of Pages
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8. DMAC - Direct Memory Access Controller
8.1 Features
* Allows High-speed data transfer
- From memory to peripheral - From memory to memory - From peripheral to memory - From peripheral to peripheral 4 Channels From 1 byte and up to 16 M bytes transfers in a single transaction Multiple addressing modes for source and destination address - Increment - Decrement - Static 1, 2, 4, or 8 bytes Burst Transfers Programmable priority between channels
* * *
* *
8.2
Overview
The XMEGA A3 has a Direct Memory Access (DMA) Controller to move data between memories and peripherals in the data space. The DMA controller uses the same data bus as the CPU to transfer data. It has 4 channels that can be configured independently. Each DMA channel can perform data transfers in blocks of configurable size from 1 to 64K bytes. A repeat counter can be used to repeat each block transfer for single transactions up to 16M bytes. Each DMA channel can be configured to access the source and destination memory address with incrementing, decrementing or static addressing. The addressing is independent for source and destination address. When the transaction is complete the original source and destination address can automatically be reloaded to be ready for the next transaction. The DMAC can access all the peripherals through their I/O memory registers, and the DMA may be used for automatic transfer of data to/from communication modules, as well as automatic data retrieval from ADC conversions, data transfer to DAC conversions, or data transfer to or from port pins. A wide range of transfer triggers is available from the peripherals, Event System and software. Each DMA channel has different transfer triggers. To allow for continuous transfers, two channels can be interlinked so that the second takes over the transfer when the first is finished and vice versa. The DMA controller can read from memory mapped EEPROM, but it cannot write to the EEPROM or access the Flash.
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9. Event System
9.1 Features
* * * *
Inter-peripheral communication and signalling with minimum latency CPU and DMA independent operation 8 Event Channels allows for up to 8 signals to be routed at the same time Events can be generated by - Timer/Counters (TCxn) - Real Time Counter (RTC) - Analog to Digital Converters (ADCx) - Analog Comparators (ACx) - Ports (PORTx) - System Clock (ClkSYS) - Software (CPU) Events can be used by - Timer/Counters (TCxn) - Analog to Digital Converters (ADCx) - Digital to Analog Converters (DACx) - Ports (PORTx) - DMA Controller (DMAC) - IR Communication Module (IRCOM) The same event can be used by multiple peripherals for synchronized timing Advanced Features - Manual Event Generation from software (CPU) - Quadrature Decoding - Digital Filtering Functions in Active and Idle mode
*
* *
*
9.2
Overview
The Event System is a set of features for inter-peripheral communication. It enables the possibility for a change of state in one peripheral to automatically trigger actions in one or more peripherals. What changes in a peripheral that will trigger actions in other peripherals are configurable by software. It is a simple, but powerful system as it allows for autonomous control of peripherals without any use of interrupts, CPU or DMA resources. The indication of a change in a peripheral is referred to as an event, and is usually the same as the interrupt conditions for that peripheral. Events are passed between peripherals using a dedicated routing network called the Event Routing Network. Figure 9-1 on page 17 shows a basic block diagram of the Event System with the Event Routing Network and the peripherals to which it is connected. This highly flexible system can be used for simple routing of signals, pin functions or for sequencing of events. The maximum latency is two CPU clock cycles from when an event is generated in one peripheral, until the actions are triggered in one or more other peripherals. The Event System is functional in both Active and Idle modes.
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Figure 9-1. Event system block diagram.
PORTx
ClkSYS
CPU
ADCx Event Routing Network DACx
RTC
ACx
IRCOM
T/Cxn
DMAC
The Event Routing Network can directly connect together ADCs, DACs, Analog Comparators (ACx), I/O ports (PORTx), the Real-time Counter (RTC), Timer/Counters (T/C) and the IR Communication Module (IRCOM). Events can also be generated from software (CPU). All events from all peripherals are always routed into the Event Routing Network. This consist of eight multiplexers where each can be configured in software to select which event to be routed into that event channel. All eight event channels are connected to the peripherals that can use events, and each of these peripherals can be configured to use events from one or more event channels to automatically trigger a software selectable action.
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10. System Clock and Clock options
10.1 Features
* Fast start-up time * Safe run-time clock switching * Internal Oscillators:
- 32 MHz run-time calibrated RC oscillator - 2 MHz run-time calibrated RC oscillator - 32.768 kHz calibrated RC oscillator - 32 kHz Ultra Low Power (ULP) oscillator External clock options - 0.4 - 16 MHz Crystal Oscillator - 32.768 kHz Crystal Oscillator - External clock PLL with internal and external clock options with 2 to 31x multiplication Clock Prescalers with 2 to 2048x division Fast peripheral clock running at 2 and 4 times the CPU clock speed Automatic Run-Time Calibration of internal oscillators Crystal Oscillator failure detection
*
* * * * *
10.2
Overview
XMEGA A3 has an advanced clock system, supporting a large number of clock sources. It incorporates both integrated oscillators, external crystal oscillators and resonators. A high frequency Phase Locked Loop (PLL) and clock prescalers can be controlled from software to generate a wide range of clock frequencies from the clock source input. It is possible to switch between clock sources from software during run-time. After reset the device will always start up running from the 2 Mhz internal oscillator. A calibration feature is available, and can be used for automatic run-time calibration of the internal 2 MHz and 32 MHz oscillators. This reduce frequency drift over voltage and temperature. A Crystal Oscillator Failure Monitor can be enabled to issue a Non-Maskable Interrupt and switch to internal oscillator if the external oscillator fails. Figure 10-1 on page 19 shows the principal clock system in XMEGA A3.
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Figure 10-1. Clock system overview
clkULP
32 kHz ULP Internal Oscillator WDT/BOD
clkRTC
32.768 kHz Calibrated Internal Oscillator 2 MHz Run-Time Calibrated Internal Oscillator 32 MHz Run-time Calibrated Internal Oscillator RTC
PERIPHERALS ADC DAC
CLOCK CONTROL clkPER UNIT with PLL and Prescaler
PORTS ... DMA INTERRUPT EVSYS RAM
32.768 KHz Crystal Oscillator
0.4 - 16 MHz Crystal Oscillator
CPU
clkCPU NVM MEMORY
External Clock Input FLASH EEPROM
Each clock source is briefly described in the following sub-sections.
10.3
10.3.1
Clock Options
32 kHz Ultra Low Power Internal Oscillator The 32 kHz Ultra Low Power (ULP) Internal Oscillator is a very low power consumption clock source. It is used for the Watchdog Timer, Brown-Out Detection and as an asynchronous clock source for the Real Time Counter. This oscillator cannot be used as the system clock source, and it cannot be directly controlled from software.
10.3.2
32.768 kHz Calibrated Internal Oscillator The 32.768 kHz Calibrated Internal Oscillator is a high accuracy clock source that can be used as the system clock source or as an asynchronous clock source for the Real Time Counter. It is calibrated during production to provide a default frequency which is close to its nominal frequency.
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10.3.3 32.768 kHz Crystal Oscillator The 32.768 kHz Crystal Oscillator is a low power driver for an external watch crystal. It can be used as system clock source or as asynchronous clock source for the Real Time Counter. 10.3.4 0.4 - 16 MHz Crystal Oscillator The 0.4 - 16 MHz Crystal Oscillator is a driver intended for driving both external resonators and crystals ranging from 400 kHz to 16 MHz. 10.3.5 2 MHz Run-time Calibrated Internal Oscillator The 2 MHz Run-time Calibrated Internal Oscillator is a high frequency oscillator. It is calibrated during production to provide a default frequency which is close to its nominal frequency. The oscillator can use the 32.768 kHz Calibrated Internal Oscillator or the 32 kHz Crystal Oscillator as a source for calibrating the frequency run-time to compensate for temperature and voltage drift hereby optimizing the accuracy of the oscillator. 10.3.6 32 MHz Run-time Calibrated Internal Oscillator The 32 MHz Run-time Calibrated Internal Oscillator is a high frequency oscillator. It is calibrated during production to provide a default frequency which is close to its nominal frequency. The oscillator can use the 32.768 kHz Calibrated Internal Oscillator or the 32 kHz Crystal Oscillator as a source for calibrating the frequency run-time to compensate for temperature and voltage drift hereby optimizing the accuracy of the oscillator. 10.3.7 External Clock input The external clock input gives the possibility to connect a clock from an external source. 10.3.8 PLL with Multiplication factor 1 - 31x The PLL provides the possibility of multiplying a frequency by any number from 1 to 31. In combination with the prescalers, this gives a wide range of output frequencies from all clock sources.
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11. Power Management and Sleep Modes
11.1 Features
* 5 sleep modes
- Idle - Power-down - Power-save - Standby - Extended standby * Power Reduction registers to disable clocks to unused peripherals
11.2
Overview
The XMEGA A3 provides various sleep modes tailored to reduce power consumption to a minimum. All sleep modes are available and can be entered from Active mode. In Active mode the CPU is executing application code. The application code decides when and which sleep mode to enter. Interrupts from enabled peripherals and all enabled reset sources can restore the microcontroller from sleep to Active mode. In addition, Power Reduction registers provide a method to stop the clock to individual peripherals from software. When this is done, the current state of the peripheral is frozen and there is no power consumption from that peripheral. This reduces the power consumption in Active mode and Idle sleep mode.
11.3
11.3.1
Sleep Modes
Idle Mode In Idle mode the CPU and Non-Volatile Memory are stopped, but all peripherals including the Interrupt Controller, Event System and DMA Controller are kept running. Interrupt requests from all enabled interrupts will wake the device.
11.3.2
Power-down Mode In Power-down mode all system clock sources, and the asynchronous Real Time Counter (RTC) clock source, are stopped. This allows operation of asynchronous modules only. The only interrupts that can wake up the MCU are the Two Wire Interface address match interrupts, and asynchronous port interrupts, e.g pin change.
11.3.3
Power-save Mode Power-save mode is identical to Power-down, with one exception: If the RTC is enabled, it will keep running during sleep and the device can also wake up from RTC interrupts.
11.3.4
Standby Mode Standby mode is identical to Power-down with the exception that all enabled system clock sources are kept running, while the CPU, Peripheral and RTC clocks are stopped. This reduces the wake-up time when external crystals or resonators are used.
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11.3.5 Extended Standby Mode Extended Standby mode is identical to Power-save mode with the exception that all enabled system clock sources are kept running while the CPU and Peripheral clocks are stopped. This reduces the wake-up time when external crystals or resonators are used.
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12. System Control and Reset
12.1 Features
* Multiple reset sources for safe operation and device reset
- Power-On Reset - External Reset - Watchdog Reset The Watchdog Timer runs from separate, dedicated oscillator - Brown-Out Reset Accurate, programmable Brown-Out levels - JTAG Reset - PDI reset - Software reset * Asynchronous reset - No running clock in the device is required for reset * Reset status register
12.2
Resetting the AVR
During reset, all I/O registers are set to their initial values. The SRAM content is not reset. Application execution starts from the Reset Vector. The instruction placed at the Reset Vector should be an Absolute Jump (JMP) instruction to the reset handling routine. By default the Reset Vector address is the lowest Flash program memory address, `0', but it is possible to move the Reset Vector to the first address in the Boot Section. The I/O ports of the AVR are immediately tri-stated when a reset source goes active. The reset functionality is asynchronous, so no running clock is required to reset the device. After the device is reset, the reset source can be determined by the application by reading the Reset Status Register.
12.3
12.3.1
Reset Sources
Power-On Reset The MCU is reset when the supply voltage VCC is below the Power-on Reset threshold voltage.
12.3.2
External Reset The MCU is reset when a low level is present on the RESET pin.
12.3.3
Watchdog Reset The MCU is reset when the Watchdog Timer period expires and the Watchdog Reset is enabled. The Watchdog Timer runs from a dedicated oscillator independent of the System Clock. For more details see "WDT - Watchdog Timer" on page 24.
12.3.4
Brown-Out Reset The MCU is reset when the supply voltage VCC is below the Brown-Out Reset threshold voltage and the Brown-out Detector is enabled. The Brown-out threshold voltage is programmable.
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12.3.5 JTAG reset The MCU is reset as long as there is a logic one in the Reset Register in one of the scan chains of the JTAG system. Refer to IEEE 1149.1 (JTAG) Boundary-scan for details. 12.3.6 PDI reset The MCU can be reset through the Program and Debug Interface (PDI). 12.3.7 Software reset The MCU can be reset by the CPU writing to a special I/O register through a timed sequence.
13. WDT - Watchdog Timer
13.1 Features
* 11 selectable timeout periods, from 8 ms to 8s. * Two operation modes
- Standard mode - Window mode * Runs from the 1 kHz output of the 32 kHz Ultra Low Power oscillator * Configuration lock to prevent unwanted changes
13.2
Overview
The XMEGA A3 has a Watchdog Timer (WDT). The WDT will run continuously when turned on and if the Watchdog Timer is not reset within a software configurable time-out period, the microcontroller will be reset. The Watchdog Reset (WDR) instruction must be run by software to reset the WDT, and prevent microcontroller reset. The WDT has a Window mode. In this mode the WDR instruction must be run within a specified period called a window. Application software can set the minimum and maximum limits for this window. If the WDR instruction is not executed inside the window limits, the microcontroller will be reset. A protection mechanism using a timed write sequence is implemented in order to prevent unwanted enabling, disabling or change of WDT settings. For maximum safety, the WDT also has an Always-on mode. This mode is enabled by programming a fuse. In Always-on mode, application software can not disable the WDT.
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14. PMIC - Programmable Multi-level Interrupt Controller
14.1 Features
* Separate interrupt vector for each interrupt * Short, predictable interrupt response time * Programmable Multi-level Interrupt Controller
- 3 programmable interrupt levels - Selectable priority scheme within low level interrupts (round-robin or fixed) - Non-Maskable Interrupts (NMI) * Interrupt vectors can be moved to the start of the Boot Section
14.2
Overview
XMEGA A3 has a Programmable Multi-level Interrupt Controller (PMIC). All peripherals can define three different priority levels for interrupts; high, medium or low. Medium level interrupts may interrupt low level interrupt service routines. High level interrupts may interrupt both lowand medium level interrupt service routines. Low level interrupts have an optional round robin scheme to make sure all interrupts are serviced within a certain amount of time. The built in oscillator failure detection mechanism can issue a Non-Maskable Interrupt (NMI).
14.3
Interrupt vectors
When an interrupt is serviced, the program counter will jump to the interrupt vector address. The interrupt vector is the sum of the peripheral's base interrupt address and the offset address for specific interrupts in each peripheral. The base addresses for the XMEGA A3 devices are shown in Table 14-1. Offset addresses for each interrupt available in the peripheral are described for each peripheral in the XMEGA A manual. For peripherals or modules that have only one interrupt, the interrupt vector is shown in Table 14-1. The program address is the word address.
Table 14-1.
Reset and Interrupt Vectors
Source RESET OSCF_INT_vect PORTC_INT_base PORTR_INT_base DMA_INT_base RTC_INT_base TWIC_INT_base TCC0_INT_base TCC1_INT_base SPIC_INT_vect USARTC0_INT_base USARTC1_INT_base AES_INT_vect Crystal Oscillator Failure Interrupt vector (NMI) Port C Interrupt base Port R Interrupt base DMA Controller Interrupt base Real Time Counter Interrupt base Two-Wire Interface on Port C Interrupt base Timer/Counter 0 on port C Interrupt base Timer/Counter 1 on port C Interrupt base SPI on port C Interrupt vector USART 0 on port C Interrupt base USART 1 on port C Interrupt base AES Interrupt vector Interrupt Description
Program Address (Base Address) 0x000 0x002 0x004 0x008 0x00C 0x014 0x018 0x01C 0x028 0x030 0x032 0x03D 0x03E
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Table 14-1. Reset and Interrupt Vectors (Continued)
Source NVM_INT_base PORTB_INT_base ACB_INT_base ADCB_INT_base PORTE_INT_base TWIE_INT_base TCE0_INT_base TCE1_INT_base SPIE_INT_vect USARTE0_INT_base USARTE1_INT_base PORTD_INT_base PORTA_INT_base ACA_INT_base ADCA_INT_base TCD0_INT_base TCD1_INT_base SPID_INT_vector USARTD0_INT_base USARTD1_INT_base PORTF_INT_base TCF0_INT_base USARTF0_INT_base Interrupt Description Non-Volatile Memory Interrupt base Port B Interrupt base Analog Comparator on Port B Interrupt base Analog to Digital Converter on Port B Interrupt base Port E INT base Two-Wire Interface on Port E Interrupt base Timer/Counter 0 on port E Interrupt base Timer/Counter 1 on port E Interrupt base SPI on port E Interrupt vector USART 0 on port E Interrupt base USART 1 on port E Interrupt base Port D Interrupt base Port A Interrupt base Analog Comparator on Port A Interrupt base Analog to Digital Converter on Port A Interrupt base Timer/Counter 0 on port D Interrupt base Timer/Counter 1 on port D Interrupt base SPI D Interrupt vector USART 0 on port D Interrupt base USART 1 on port D Interrupt base Port F Interrupt base Timer/Counter 0 on port F Interrupt base USART 0 on port F Interrupt base
Program Address (Base Address) 0x040 0x044 0x048 0x04E 0x056 0x05A 0x05E 0x06A 0x072 0x074 0x07A 0x080 0x084 0x088 0x08E 0x09A 0x0A6 0x0AE 0x0B0 0x0B6 0x0D0 0x0D8 0x0EE
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15. I/O Ports
15.1 Features
* Selectable input and output configuration for each pin individually * Flexible pin configuration through dedicated Pin Configuration Register * Synchronous and/or asynchronous input sensing with port interrupts and events
- Sense both edges - Sense rising edges - Sense falling edges - Sense low level Asynchronous wake-up from all input sensing configurations Two port interrupts with flexible pin masking Highly configurable output driver and pull settings: - Totem-pole - Pull-up/-down - Wired-AND - Wired-OR - Bus-keeper - Inverted I/O Configuration of multiple pins in a single operation Read-Modify-Write (RMW) support Toggle/clear/set registers for Output and Direction registers Clock output on port pin Event Channel 7 output on port pin Mapping of port registers (virtual ports) into bit accessible I/O memory space
* * *
* * * * * *
15.2
Overview
The XMEGA A3 devices have flexible General Purpose I/O Ports. A port consists of up to 8 pins, ranging from pin 0 to pin 7. The ports implement several functions, including synchronous/asynchronous input sensing, pin change interrupts and configurable output settings. All functions are individual per pin, but several pins may be configured in a single operation.
15.3
I/O configuration
All port pins (Pn) have programmable output configuration. In addition, all port pins have an inverted I/O function. For an input, this means inverting the signal between the port pin and the pin register. For an output, this means inverting the output signal between the port register and the port pin. The inverted I/O function can be used also when the pin is used for alternate functions.
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15.3.1 Push-pull Figure 15-1. I/O configuration - Totem-pole
DIRn OUTn INn Pn
15.3.2
Pull-down Figure 15-2. I/O configuration - Totem-pole with pull-down (on input)
DIRn OUTn INn Pn
15.3.3
Pull-up Figure 15-3. I/O configuration - Totem-pole with pull-up (on input)
DIRn
OUTn INn
15.3.4 Bus-keeper
Pn
The bus-keeper's weak output produces the same logical level as the last output level. It acts as a pull-up if the last level was `1', and pull-down if the last level was `0'.
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Figure 15-4. I/O configuration - Totem-pole with bus-keeper
DIRn OUTn INn
Pn
15.3.5
Others Figure 15-5. Output configuration - Wired-OR with optional pull-down
OUTn Pn INn
Figure 15-6. I/O configuration - Wired-AND with optional pull-up
INn Pn OUTn
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15.4 Input sensing
* * * *
Sense both edges Sense rising edges Sense falling edges Sense low level
Input sensing is synchronous or asynchronous depending on the enabled clock for the ports, and the configuration is shown in Figure 15-7 on page 30. Figure 15-7. Input sensing system overview
Asynchronous sensing
EDGE DETECT
Interrupt Control
IREQ
Synchronous sensing Pn Synchronizer
INn D QD Q
EDGE DETECT
Event
INVERTED I/O
R
R
When a pin is configured with inverted I/O, the pin value is inverted before the input sensing.
15.5
Port Interrupt
Each port has two interrupts with separate priority and interrupt vector. All pins on the port can be individually selected as source for each of the interrupts. The interrupts are then triggered according to the input sense configuration for each pin configured as source for the interrupt.
15.6
Alternate Port Functions
In addition to the input/output functions on all port pins, most pins have alternate functions. This means that other modules or peripherals connected to the port can use the port pins for their functions, such as communication or pulse-width modulation. "Pinout and Pin Functions" on page 49 shows which modules on peripherals that enable alternate functions on a pin, and which alternate functions that are available on a pin.
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16. T/C - 16-bits Timer/Counter with PWM
16.1 Features
* Seven 16-bit Timer/Counters
- Four Timer/Counters of type 0 - Three Timer/Counters of type 1 Four Compare or Capture (CC) Channels in Timer/Counter 0 Two Compare or Capture (CC) Channels in Timer/Counter 1 Double Buffered Timer Period Setting Double Buffered Compare or Capture Channels Waveform Generation: - Single Slope Pulse Width Modulation - Dual Slope Pulse Width Modulation - Frequency Generation Input Capture: - Input Capture with Noise Cancelling - Frequency capture - Pulse width capture - 32-bit input capture Event Counter with Direction Control Timer Overflow and Timer Error Interrupts and Events One Compare Match or Capture Interrupt and Event per CC Channel Supports DMA Operation Hi-Resolution Extension (Hi-Res) Advanced Waveform Extension (AWEX)
* * * * *
*
* * * * * *
16.2
Overview
XMEGA A3 has seven Timer/Counters, four Timer/Counter 0 and three Timer/Counter 1. The difference between them is that Timer/Counter 0 has four Compare/Capture channels, while Timer/Counter 1 has two Compare/Capture channels. The Timer/Counters (T/C) are 16-bit and can count any clock, event or external input in the microcontroller. A programmable prescaler is available to get a useful T/C resolution. Updates of Timer and Compare registers are double buffered to ensure glitch free operation. Single slope PWM, dual slope PWM and frequency generation waveforms can be generated using the Compare Channels. Through the Event System, any input pin or event in the microcontroller can be used to trigger input capture, hence no dedicated pins is required for this. The input capture has a noise canceller to avoid incorrect capture of the T/C, and can be used to do frequency and pulse width measurements. A wide range of interrupt or event sources are available, including T/C Overflow, Compare match and Capture for each Compare/Capture channel in the T/C. PORTC, PORTD and PORTE each has one Timer/Counter 0 and one Timer/Counter1. PORTF has one Timer/Counter 0. Notation of these are TCC0 (Time/Counter C0), TCC1, TCD0, TCD1, TCE0, TCE1 and TCF0, respectively.
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Figure 16-1. Overview of a Timer/Counter and closely related peripherals
Timer/Counter Base Counter
Timer Period Control Logic Counter
Prescaler Event System
clkPER
clkPER4 Compare/Capture Channel D Compare/Capture Channel C Compare/Capture Channel B Compare/Capture Channel A
Comparator Buffer
Capture Control Waveform Generation
AWeX Hi-Res
DTI Dead-Time Insertion
Pattern Generation Fault Protection
The Hi-Resolution Extension can be enabled to increase the waveform generation resolution by 2 bits (4x). This is available for all Timer/Counters. See "Hi-Res - High Resolution Extension" on page 34 for more details. The Advanced Waveform Extension can be enabled to provide extra and more advanced features for the Timer/Counter. This are only available for Timer/Counter 0. See "AWEX - Advanced Waveform Extension" on page 33 for more details.
PORT
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17. AWEX - Advanced Waveform Extension
17.1 Features
* * * * * * * *
Output with complementary output from each Capture channel Four Dead Time Insertion (DTI) Units, one for each Capture channel 8-bit DTI Resolution Separate High and Low Side Dead-Time Setting Double Buffered Dead-Time Event Controlled Fault Protection Single Channel Multiple Output Operation (for BLDC motor control) Double Buffered Pattern Generation
17.2
Overview
The Advanced Waveform Extension (AWEX) provides extra features to the Timer/Counter in Waveform Generation (WG) modes. The AWEX enables easy and safe implementation of for example, advanced motor control (AC, BLDC, SR, and Stepper) and power control applications. Any WG output from a Timer/Counter 0 is split into a complimentary pair of outputs when any AWEX feature is enabled. These output pairs go through a Dead-Time Insertion (DTI) unit that enables generation of the non-inverted Low Side (LS) and inverted High Side (HS) of the WG output with dead time insertion between LS and HS switching. The DTI output will override the normal port value according to the port override setting. Optionally the final output can be inverted by using the invert I/O setting for the port pin. The Pattern Generation unit can be used to generate a synchronized bit pattern on the port it is connected to. In addition, the waveform generator output from Compare Channel A can be distributed to, and override all port pins. When the Pattern Generator unit is enabled, the DTI unit is bypassed. The Fault Protection unit is connected to the Event System. This enables any event to trigger a fault condition that will disable the AWEX output. Several event channels can be used to trigger fault on several different conditions. The AWEX is available for TCC0. The notation of this is AWEXC.
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18. Hi-Res - High Resolution Extension
18.1 Features
* Increases Waveform Generator resolution by 2-bits (4x) * Supports Frequency, single- and dual-slope PWM operation * Supports the AWEX when this is enabled and used for the same Timer/Counter
18.2
Overview
The Hi-Resolution (Hi-Res) Extension is able to increase the resolution of the waveform generation output by a factor of 4. When enabled for a Timer/Counter, the Fast Peripheral clock running at four times the CPU clock speed will be as input to the Timer/Counter. The High Resolution Extension can also be used when an AWEX is enabled and used with a Timer/Counter. XMEGA A3 devices have four Hi-Res Extensions that each can be enabled for each Timer/Counters pair on PORTC, PORTD, PORTE and PORTF. The notation of these are HIRESC, HIRESD, HIRESE and HIRESF, respectively.
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19. RTC - Real-Time Counter
19.1 Features
* * * * * *
16-bit Timer Flexible Tick resolution ranging from 1 Hz to 32.768 kHz One Compare register One Period register Clear timer on Overflow or Compare Match Overflow or Compare Match event and interrupt generation
19.2
Overview
The XMEGA A3 includes a 16-bit Real-time Counter (RTC). The RTC can be clocked from an accurate 32.768 kHz Crystal Oscillator, the 32.768 kHz Calibrated Internal Oscillator, or from the 32 kHz Ultra Low Power Internal Oscillator. The RTC includes both a Period and a Compare register. For details, see Figure 19-1. A wide range of Resolution and Time-out periods can be configured using the RTC. With a maximum resolution of 30.5 s, time-out periods range up to 2000 seconds. With a resolution of 1 second, the maximum time-out period is over 18 hours (65536 seconds). Figure 19-1. Real-time Counter overview
Period Overflow 32.768 kHz 10-bit prescaler 1.024 kHz = = Counter
Compare Match Compare
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20. TWI - Two Wire Interface
20.1 Features
* * * * * * * * * * * *
Two Identical TWI peripherals Simple yet Powerful and Flexible Communication Interface Both Master and Slave Operation Supported Device can Operate as Transmitter or Receiver 7-bit Address Space Allows up to 128 Different Slave Addresses Multi-master Arbitration Support Up to 400 kHz Data Transfer Speed Slew-rate Limited Output Drivers Noise Suppression Circuitry Rejects Spikes on Bus Lines Fully Programmable Slave Address with General Call Support Address Recognition Causes Wake-up when in Sleep Mode I2C and System Management Bus (SMBus) compatible
20.2
Overview
The Two-Wire Interface (TWI) is a bi-directional wired-AND bus with only two lines, the clock (SCL) line and the data (SDA) line. The protocol makes it possible to interconnect up to 128 individually addressable devices. Since it is a multi-master bus, one or more devices capable of taking control of the bus can be connected. The only external hardware needed to implement the bus is a single pull-up resistor for each of the TWI bus lines. Mechanisms for resolving bus contention are inherent in the TWI protocol. PORTC and PORTE each has one TWI. Notation of these peripherals are TWIC and TWIE.
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21. SPI - Serial Peripheral Interface
21.1 Features
* * * * * * * * *
Three Identical SPI peripherals Full-duplex, Three-wire Synchronous Data Transfer Master or Slave Operation LSB First or MSB First Data Transfer Seven Programmable Bit Rates End of Transmission Interrupt Flag Write Collision Flag Protection Wake-up from Idle Mode Double Speed (CK/2) Master SPI Mode
21.2
Overview
The Serial Peripheral Interface (SPI) allows high-speed full-duplex, synchronous data transfer between different devices. Devices can communicate using a master-slave scheme, and data is transferred both to and from the devices simultaneously. PORTC, PORTD, and PORTE each has one SPI. Notation of these peripherals are SPIC, SPID, and SPIE respectively.
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22. USART
22.1 Features
* * * * * * * * * * * * * * *
Seven Identical USART peripherals Full Duplex Operation (Independent Serial Receive and Transmit Registers) Asynchronous or Synchronous Operation Master or Slave Clocked Synchronous Operation High-resolution Arithmetic Baud Rate Generator Supports Serial Frames with 5, 6, 7, 8, or 9 Data Bits and 1 or 2 Stop Bits Odd or Even Parity Generation and Parity Check Supported by Hardware Data OverRun Detection Framing Error Detection Noise Filtering Includes False Start Bit Detection and Digital Low Pass Filter Three Separate Interrupts on TX Complete, TX Data Register Empty and RX Complete Multi-processor Communication Mode Double Speed Asynchronous Communication Mode Master SPI mode for SPI communication IrDA support through the IRCOM module
22.2
Overview
The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART) is a highly flexible serial communication module. The USART supports full duplex communication, and both asynchronous and clocked synchronous operation. The USART can also be set in Master SPI mode to be used for SPI communication. Communication is frame based, and the frame format can be customized to support a wide range of standards. The USART is buffered in both direction, enabling continued data transmission without any delay between frames. There are separate interrupt vectors for receive and transmit complete, enabling fully interrupt driven communication. Frame error and buffer overflow are detected in hardware and indicated with separate status flags. Even or odd parity generation and parity check can also be enabled. One USART can use the IRCOM module to support IrDA 1.4 physical compliant pulse modulation and demodulation for baud rates up to 115.2 kbps. PORTC, PORTD, and PORTE each has two USARTs, while PORTF has one USART only. Notation of these peripherals are USARTC0, USARTC1, USARTD0, USARTD1, USARTE0, USARTE1 and USARTF0, respectively.
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23. IRCOM - IR Communication Module
23.1 Features
* Pulse modulation/demodulation for infrared communication * Compatible to IrDA 1.4 physical for baud rates up to 115.2 kbps * Selectable pulse modulation scheme
- 3/16 of baud rate period - Fixed pulse period, 8-bit programmable - Pulse modulation disabled * Built in filtering * Can be connected to and used by one USART at a time
23.2
Overview
XMEGA contains an Infrared Communication Module (IRCOM) for IrDA communication with baud rates up to 115.2 kbps. This supports three modulation schemes: 3/16 of baud rate period, fixed programmable pulse time based on the Peripheral Clock speed, or pulse modulation disabled. There is one IRCOM available which can be connected to any USART to enable infrared pulse coding/decoding for that USART.
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24. Crypto Engine
24.1 Features
* Data Encryption Standard (DES) CPU instruction * Advanced Encryption Standard (AES) Crypto module * DES Instruction
- Encryption and Decryption - Single-cycle DES instruction - Encryption/Decryption in 16 clock cycles per 8-byte block * AES Crypto Module - Encryption and Decryption - Support 128-bit keys - Support XOR data load mode to the State memory for Cipher Block Chaining - Encryption/Decryption in 375 clock cycles per 16-byte block
24.2
Overview
The Advanced Encryption Standard (AES) and Data Encryption Standard (DES) are two commonly used encryption standards. These are supported through an AES peripheral module and a DES CPU instruction. All communication interfaces and the CPU can optionally use AES and DES encrypted communication and data storage. DES is supported by a DES instruction in the AVR XMEGA CPU. The 8-byte key and 8-byte data blocks must be loaded into the Register file, and then DES must be executed 16 times to encrypt/decrypt the data block. The AES Crypto Module encrypts and decrypts 128-bit data blocks with the use of a 128-bit key. The key and data must be loaded into the key and state memory in the module before encryption/decryption is started. It takes 375 peripheral clock cycles before the encryption/decryption is done and decrypted/encrypted data can be read out, and an optional interrupt can be generated. The AES Crypto Module also has DMA support with transfer triggers when encryption/decryption is done and optional auto-start of encryption/decryption when the state memory is fully loaded.
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25. ADC - 12-bit Analog to Digital Converter
25.1 Features
* * * * * * *
Two ADCs with 12-bit resolution 2 Msps sample rate for each ADC Signed and Unsigned conversions 4 result registers with individual input channel control for each ADC 8 single ended inputs for each ADC 8x4 differential inputs for each ADC 4 internal inputs: - Integrated Temperature Sensor - DAC Output - VCC voltage divided by 10 - Bandgap voltage Software selectable gain of 2, 4, 8, 16, 32 or 64 Software selectable resolution of 8- or 12-bit. Internal or External Reference selection Event triggered conversion for accurate timing DMA transfer of conversion results Interrupt/Event on compare result
* * * * * *
25.2
Overview
XMEGA A3 devices have two Analog to Digital Converters (ADC), see Figure 25-1 on page 42. The two ADC modules can be operated simultaneously, individually or synchronized. The ADC converts analog voltages to digital values. The ADC has 12-bit resolution and is capable of converting up to 2 million samples per second. The input selection is flexible, and both single-ended and differential measurements can be done. For differential measurements an optional gain stage is available to increase the dynamic range. In addition several internal signal inputs are available. The ADC can provide both signed and unsigned results. This is a pipeline ADC. A pipeline ADC consists of several consecutive stages, where each stage convert one part of the result. The pipeline design enables high sample rate at low clock speeds, and remove limitations on samples speed versus propagation delay. This also means that a new analog voltage can be sampled and a new ADC measurement started while other ADC measurements are ongoing. ADC measurements can either be started by application software or an incoming event from another peripheral in the device. Four different result registers with individual input selection (MUX selection) are provided to make it easier for the application to keep track of the data. Each result register and MUX selection pair is referred to as an ADC Channel. It is possible to use DMA to move ADC results directly to memory or peripherals when conversions are done. Both internal and external analog reference voltages can be used. An accurate internal 1.0V reference is available. An integrated temperature sensor is available and the output from this can be measured with the ADC. The output from the DAC, VCC/10 and the Bandgap voltage can also be measured by the ADC.
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Figure 25-1. ADC overview
Channel A MUX selection Channel B MUX selection Channel C MUX selection Internal inputs Channel D MUX selection
Configuration Reference selection
Channel A Register Channel B Register
Pin inputs
ADC Channel C Register Channel D Register
Pin inputs
1-64 X
Event Trigger
Each ADC has four MUX selection registers with a corresponding result register. This means that four channels can be sampled within 1.5 s without any intervention by the application other than starting the conversion. The results will be available in the result registers. The ADC may be configured for 8- or 12-bit result, reducing the minimum conversion time (propagation delay) from 3.5 s for 12-bit to 2.5 s for 8-bit result. ADC conversion results are provided left- or right adjusted with optional `1' or `0' padding. This eases calculation when the result is represented as a signed integer (signed 16-bit number). PORTA and PORTB each has one ADC. Notation of these peripherals are ADCA and ADCB, respectively.
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26. DAC - 12-bit Digital to Analog Converter
26.1 Features
* * * * * * * *
One DAC with 12-bit resolution Up to 1 Msps conversion rate for each DAC Flexible conversion range Multiple trigger sources 1 continuous output or 2 Sample and Hold (S/H) outputs for each DAC Built-in offset and gain calibration High drive capabilities Low Power Mode
26.2
Overview
The XMEGA A3 features one two-channel, 12-bit, 1 Msps DACs with built-in offset and gain calibration, see Figure 26-1 on page 43. A DAC converts a digital value into an analog signal. The DAC may use an internal 1.1 voltage as the upper limit for conversion, but it is also possible to use the supply voltage or any applied voltage in-between. The external reference input is shared with the ADC reference input. Figure 26-1. DAC overview
Configuration Reference selection
Channel A Register
Channel A
DAC
Channel B Register Channel B
Event Trigger
The DAC has one continuous output with high drive capabilities for both resistive and capacitive loads. It is also possible to split the continuous time channel into two Sample and Hold (S/H) channels, each with separate data conversion registers. A DAC conversion may be started from the application software by writing the data conversion registers. The DAC can also be configured to do conversions triggered by the Event System to have regular timing, independent of the application software. DMA may be used for transferring data from memory locations to DAC data registers. The DAC has a built-in calibration system to reduce offset and gain error when loading with a calibration value from software. PORTB each has one DAC. Notation of this peripheral is DACB.
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27. AC - Analog Comparator
27.1 Features
* Four Analog Comparators * Selectable Power vs. Speed * Selectable hysteresis
- 0, 20 mV, 50 mV
* Analog Comparator output available on pin * Flexible Input Selection
- All pins on the port - Output from the DAC - Bandgap reference voltage. - Voltage scaler that can perform a 64-level scaling of the internal VCC voltage. * Interrupt and event generation on - Rising edge - Falling edge - Toggle * Window function interrupt and event generation on - Signal above window - Signal inside window - Signal below window
27.2
Overview
XMEGA A3 features four Analog Comparators (AC). An Analog Comparator compares two voltages, and the output indicates which input is largest. The Analog Comparator may be configured to give interrupt requests and/or events upon several different combinations of input change. Both hysteresis and propagation delays may be adjusted in order to find the optimal operation for each application. A wide range of input selection is available, both external pins and several internal signals can be used. The Analog Comparators are always grouped in pairs (AC0 and AC1) on each analog port. They have identical behavior but separate control registers. Optionally, the state of the comparator is directly available on a pin. PORTA and PORTB each has one AC pair. Notations are ACA and ACB, respectively.
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Figure 27-1. Analog comparator overview
Pin inputs Internal inputs + AC0 Pin inputs Internal inputs VCC scaled Interrupt sensitivity control Interrupts Events Pin 0 output
Pin inputs Internal inputs + AC1 Pin inputs Internal inputs VCC scaled -
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27.3 Input Selection
The Analog comparators have a very flexible input selection and the two comparators grouped in a pair may be used to realize a window function. One pair of analog comparators is shown in Figure 27-1 on page 45. * Input selection from pin
- Pin 0, 1, 2, 3, 4, 5, 6 selectable to positive input of analog comparator - Pin 0, 1, 3, 5, 7 selectable to negative input of analog comparator * Internal signals available on positive analog comparator inputs - Output from 12-bit DAC * Internal signals available on negative analog comparator inputs - 64-level scaler of the VCC, available on negative analog comparator input - Bandgap voltage reference * Output from 12-bit DAC
27.4
Window Function
The window function is realized by connecting the external inputs of the two analog comparators in a pair as shown in Figure 27-2. Figure 27-2. Analog comparator window function
+ AC0 Upper limit of window Input signal Interrupt sensitivity control + AC1 Lower limit of window Interrupts Events
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28. OCD - On-chip Debug
28.1 Features
* Complete Program Flow Control
- Go, Stop, Reset, Step into, Step over, Step out, Run-to-Cursor Debugging on C and high-level language source code level Debugging on Assembler and disassembler level 1 dedicated program address or source level breakpoint for AVR Studio / debugger 4 Hardware Breakpoints Unlimited Number of User Program Breakpoints Unlimited Number of User Data Breakpoints, with break on: - Data location read, write or both read and write - Data location content equal or not equal to a value - Data location content is greater or less than a value - Data location content is within or outside a range - Bits of a data location are equal or not equal to a value * Non-Intrusive Operation - No hardware or software resources in the device are used * High Speed Operation - No limitation on debug/programming clock frequency versus system clock frequency
* * * * * *
28.2
Overview
The XMEGA A3 has a powerful On-Chip Debug (OCD) system that - in combination with Atmel's development tools - provides all the necessary functions to debug an application. It has support for program and data breakpoints, and can debug an application from C and high level language source code level, as well as assembler and disassembler level. It has full Non-Intrusive Operation and no hardware or software resources in the device are used. The ODC system is accessed through an external debugging tool which connects to the JTAG or PDI physical interfaces. Refer to "Program and Debug Interfaces" on page 48.
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29. Program and Debug Interfaces
29.1 Features
* * * * *
PDI - Program and Debug Interface (Atmel proprietary 2-pin interface) JTAG Interface (IEEE std. 1149.1 compliant) Boundary-scan capabilities according to the IEEE Std. 1149.1 (JTAG) Access to the OCD system Programming of Flash, EEPROM, Fuses and Lock Bits
29.2
Overview
The programming and debug facilities are accessed through the JTAG and PDI physical interfaces. The PDI physical interface uses one dedicated pin together with the Reset pin, and no general purpose pins are used. JTAG uses four general purpose pins on PORTB.
29.3
JTAG interface
The JTAG physical layer handles the basic low-level serial communication over four I/O lines named TMS, TCK, TDI, and TDO. It complies to the IEEE Std. 1149.1 for test access port and boundary scan.
29.4
PDI - Program and Debug Interface
The PDI is an Atmel proprietary protocol for communication between the microcontroller and Atmel's development tools.
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30. Pinout and Pin Functions
The pinout of XMEGA A3 is shown in "" on page 2. In addition to general I/O functionality, each pin may have several function. This will depend on which peripheral is enabled and connected to the actual pin. Only one of the alternate pin functions can be used at time.
30.1
30.1.1
Alternate Pin Function Description
The tables below show the notation for all pin functions available and describe its function. Operation/Power Supply
VCC AVCC GND Digital supply voltage Analog supply voltage Ground
30.1.2
Port Interrupt functions
SYNC ASYNC Port pin with full synchronous and limited asynchronous interrupt function Port pin with full synchronous and full asynchronous interrupt function
30.1.3
Analog functions
ACn AC0OUT ADCn DACn AREF Analog Comparator input pin n Analog Comparator 0 Output Analog to Digital Converter input pin n Digital to Analog Converter output pin n Analog Reference input pin
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30.1.4 Timer/Counter and AWEX functions
OCnx OCxn Output Compare Channel x for Timer/Counter n Inverted Output Compare Channel x for Timer/Counter n
30.1.5
Communication functions
SCL SDA SCLIN SCLOUT SDAIN SDAOUT XCKn RXDn TXDn SS MOSI MISO SCK Serial Clock for TWI Serial Data for TWI Serial Clock In for TWI when external driver interface is enabled Serial Clock Out for TWI when external driver interface is enabled Serial Data In for TWI when external driver interface is enabled Serial Data Out for TWI when external driver interface is enabled Transfer Clock for USART n Receiver Data for USART n Transmitter Data for USART n Slave Select for SPI Master Out Slave In for SPI Master In Slave Out for SPI Serial Clock for SPI
30.1.6
Oscillators, Clock and Event
TOSCn XTALn CLKOUT EVOUT Timer Oscillator pin n Input/Output for inverting Oscillator pin n Peripheral Clock Output Event Channel 0 Output
30.1.7
Debug/System functions
RESET PDI_CLK PDI_DATA TCK TDI TDO TMS
Reset pin Program and Debug Interface Clock pin Program and Debug Interface Data pin JTAG Test Clock JTAG Test Data In JTAG Test Data Out JTAG Test Mode Select
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30.2
Alternate Pin Functions
The tables below show the main and alternate pin functions for all pins on each port. They also show which peripheral that makes use of or enables the alternate pin function.
Table 30-1.
PORT A GND AVCC PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PIN # 60 61 62 63 64 1 2 3 4 5
Port A - Alternate functions
INTERRUPT ADCA POS ADCA NEG ADAA GAINPOS ADCA GAINNEG ACA POS ACA NEG ACA OUT REFA
SYNC SYNC SYNC/ASYNC SYNC SYNC SYNC SYNC SYNC
ADC0 ADC1 ADC2 ADC3 ADC4 ADC5 ADC6 ADC7
ADC0 ADC1 ADC2 ADC3
ADC0 ADC1 ADC2 ADC3 ADC4 ADC5 ADC6 ADC7 ADC4 ADC5 ADC6 ADC7
AC0 AC1 AC2 AC3 AC4 AC5 AC6
AC0 AC1
AREF
AC3
AC5
AC7
AC0 OUT
Table 30-2.
PORT B PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 GND VCC PIN # 6 7 8 9 10 11 12 13 14 15
Port B - Alternate functions
INTERRUPT SYNC SYNC SYNC/ASYNC SYNC SYNC SYNC SYNC SYNC ADCB POS ADC0 ADC1 ADC2 ADC3 ADC4 ADC5 ADC6 ADC7 ADCB NEG ADC0 ADC1 ADC2 ADC3 ADCB GAINPOS ADC0 ADC1 ADC2 ADC3 ADC4 ADC5 ADC6 ADC7 ADC4 ADC5 ADC6 ADC7 ADCB GAINNEG ACB POS AC0 AC1 AC2 AC3 AC4 AC5 AC6 AC7 AC0 OUT AC5 AC3 ACB NEG AC0 AC1 DAC0 DAC1 TMS TDI TCK TDO ACB OUT DACB REFB AREF JTAG
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Table 30-3.
PORT C PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 GND VCC PIN # 16 17 18 19 20 21 22 23 24 25
Port C - Alternate functions
INTERRUPT SYNC SYNC SYNC/ASYNC SYNC SYNC SYNC SYNC SYNC TCC0 OC0A OC0B OC0C OC0D AWEXC OC0A OC0A OC0B OC0B OC0C OC0C OC0D OC0D OC1A OC1B XCK1 RXD1 TXD1 XCK0 RXD0 TXD0 SS MOSI MISO SCK CLKOUT EVOUT TCC1 USARTC0 USARTC1 SPIC TWIC SDA SCL CLOCKOUT EVENTOUT
Table 30-4.
PORT D PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 GND VCC PIN # 26 27 28 29 30 31 32 33 34 35
Port D - Alternate functions
INTERRUPT SYNC SYNC SYNC/ASYNC SYNC SYNC SYNC SYNC SYNC TCD0 OC0A OC0B OC0C OC0D OC1A OC1B XCK1 RXD1 TXD1 XCK0 RXD0 TXD0 SS MOSI MISO SCK CLKOUT EVOUT TCD1 USARTD0 USARTD1 SPID CLOCKOUT EVENTOUT
Table 30-5.
PORT E PE0 PE1 PE2 PE3 PE4 PE5 PE6 PE7 GND VCC PIN # 36 37 38 39 40 41 42 43 44 45
Port E - Alternate functions
INTERRUPT SYNC SYNC SYNC/ASYNC SYNC SYNC SYNC SYNC SYNC TCE0 OC0A OC0B OC0C OC0D OC1A OC1B XCK1 RXD1 TXD1 XCK0 RXD0 TXD0 SS MOSI MISO SCK CLKOUT EVOUT TOSC2 TOSC1 TCE1 USARTE0 USARTE1 SPIE TWIE SDA SCL CLOCKOUT EVENTOUT TOSC
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Table 30-6.
PORT F PF0 PF1 PF2 PF3 PF4 PF5 PF6 PF7 GND VCC
Port F - Alternate functions
PIN # 46 47 48 49 50 51 54 55 52 53 INTERRUPT SYNC SYNC SYNC/ASYNC SYNC SYNC SYNC SYNC SYNC TCF0 OC0A OC0B OC0C OC0D XCK0 RXD0 TXD0 USARTF0
Table 30-7.
PORT R PDI RESET PRO PR1 PIN # 56 57 58 59 SYNC SYNC INTERRUPT
Port R - Alternate functions
PROGR PDI_DATA PDI_CLOCK XTAL2 XTAL1 XTAL
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31. Peripheral Module Address Map
The address maps show the base address for each peripheral and module in XMEGA A3. For complete register description and summary for each peripheral module, refer to the XMEGA A Manual.
Base Address
0x0000 0x0010 0x0014 0x0018 0x001C 0x0030 0x0040 0x0048 0x0050 0x0060 0x0068 0x0070 0x0078 0x0080 0x0090 0x00A0 0x00B0 0x00C0 0x0100 0x0180 0x01C0 0x0200 0x0240 0x0320 0x0380 0x0390 0x0400 0x0480 0x04A0 0x0600 0x0620 0x0640 0x0660 0x0680 0x06A0 0x07E0 0x0800 0x0840 0x0880 0x0890 0x08A0 0x08B0 0x08C0 0x08F8 0x0900 0x0940 0x0990 0x09A0 0x09B0 0x09C0 0x0A00 0x0A40 0x0A80 0x0A90 0x0AA0 0x0AB0 0x0AC0 0x0B00 0x0B90 0x0BA0
Name
GPIO VPORT0 VPORT1 VPORT2 VPORT3 CPU CLK SLEEP OSC DFLLRC32M DFLLRC2M PR RST WDT MCU PMIC PORTCFG AES DMA EVSYS NVM ADCA ADCB DACB ACA ACB RTC TWIC TWIE PORTA PORTB PORTC PORTD PORTE PORTF PORTR TCC0 TCC1 AWEXC HIRESC USARTC0 USARTC1 SPIC IRCOM TCD0 TCD1 HIRESD USARTD0 USARTD1 SPID TCE0 TCE1 AWEXE HIRESE USARTE0 USARTE1 SPIE TCF0 HIRESF USARTF0
Description
General Purpose IO Registers Virtual Port 0 Virtual Port 1 Virtual Port 2 Virtual Port 2 CPU Clock Control Sleep Controller Oscillator Control DFLL for the 32 MHz Internal RC Oscillator DFLL for the 2 MHz RC Oscillator Power Reduction Reset Controller Watch-Dog Timer MCU Control Programmable MUltilevel Interrupt Controller Port Configuration AES Module DMA Controller Event System Non Volatile Memory (NVM) Controller Analog to Digital Converter on port A Analog to Digital Converter on port B Digital to Analog Converter on port B Analog Comparator pair on port A Analog Comparator pair on port B Real Time Counter Two Wire Interface on port C Two Wire Interfaceon port E Port A Port B Port C Port D Port E Port F Port R Timer/Counter 0 on port C Timer/Counter 1 on port C Advanced Waveform Extension on port C High Resolution Extension on port C USART 0 on port C USART 1 on port C Serial Peripheral Interface on port C Infrared Communication Module Timer/Counter 0 on port D Timer/Counter 1 on port D High Resolution Extension on port D USART 0 on port D USART 1 on port D Serial Peripheral Interface on port D Timer/Counter 0 on port E Timer/Counter 1 on port E Advanced Waveform Extensionon port E High Resolution Extension on port E USART 0 on port E USART 1 on oirt E Serial Peripheral Interface on port E Timer/Counter 0 on port F High Resolution Extension on port F USART 0 on port F
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32. Instruction Set Summary
Mnemonics Operands Description Arithmetic and Logic Instructions ADD ADC ADIW SUB SUBI SBC SBCI SBIW AND ANDI OR ORI EOR COM NEG SBR CBR INC DEC TST CLR SER MUL MULS MULSU FMUL FMULS FMULSU DES Rd, Rr Rd, Rr Rd, K Rd, Rr Rd, K Rd, Rr Rd, K Rd, K Rd, Rr Rd, K Rd, Rr Rd, K Rd, Rr Rd Rd Rd,K Rd,K Rd Rd Rd Rd Rd Rd,Rr Rd,Rr Rd,Rr Rd,Rr Rd,Rr Rd,Rr K Add without Carry Add with Carry Add Immediate to Word Subtract without Carry Subtract Immediate Subtract with Carry Subtract Immediate with Carry Subtract Immediate from Word Logical AND Logical AND with Immediate Logical OR Logical OR with Immediate Exclusive OR One's Complement Two's Complement Set Bit(s) in Register Clear Bit(s) in Register Increment Decrement Test for Zero or Minus Clear Register Set Register Multiply Unsigned Multiply Signed Multiply Signed with Unsigned Fractional Multiply Unsigned Fractional Multiply Signed Fractional Multiply Signed with Unsigned Data Encryption Rd Rd Rd Rd Rd Rd Rd Rd + 1:Rd Rd Rd Rd Rd Rd Rd Rd Rd Rd Rd Rd Rd Rd Rd R1:R0 R1:R0 R1:R0 R1:R0 R1:R0 R1:R0 if (H = 0) then R15:R0 else if (H = 1) then R15:R0 Branch Instructions RJMP IJMP EIJMP JMP RCALL ICALL EICALL k k k Relative Jump Indirect Jump to (Z) Extended Indirect Jump to (Z) Jump Relative Call Subroutine Indirect Call to (Z) Extended Indirect Call to (Z) PC PC(15:0) PC(21:16) PC(15:0) PC(21:16) PC PC PC(15:0) PC(21:16) PC(15:0) PC(21:16) PC + k + 1 Z, 0 Z, EIND k PC + k + 1 Z, 0 Z, EIND None None None None None None None 2 2 2 3 2 / 3(1) 2 / 3(1) 3(1) Rd + Rr Rd + Rr + C Rd + 1:Rd + K Rd - Rr Rd - K Rd - Rr - C Rd - K - C Rd + 1:Rd - K Rd * Rr Rd * K Rd v Rr Rd v K Rd Rr $FF - Rd $00 - Rd Rd v K Rd * ($FFh - K) Rd + 1 Rd - 1 Rd * Rd Rd Rd $FF Rd x Rr (UU) Rd x Rr (SS) Rd x Rr (SU) Rd x Rr<<1 (UU) Rd x Rr<<1 (SS) Rd x Rr<<1 (SU) Encrypt(R15:R0, K) Decrypt(R15:R0, K) Z,C,N,V,S,H Z,C,N,V,S,H Z,C,N,V,S Z,C,N,V,S,H Z,C,N,V,S,H Z,C,N,V,S,H Z,C,N,V,S,H Z,C,N,V,S Z,N,V,S Z,N,V,S Z,N,V,S Z,N,V,S Z,N,V,S Z,C,N,V,S Z,C,N,V,S,H Z,N,V,S Z,N,V,S Z,N,V,S Z,N,V,S Z,N,V,S Z,N,V,S None Z,C Z,C Z,C Z,C Z,C Z,C 1 1 2 1 1 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 1/2 Operation Flags #Clocks
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Mnemonics CALL RET RETI CPSE CP CPC CPI SBRC SBRS SBIC SBIS BRBS BRBC BREQ BRNE BRCS BRCC BRSH BRLO BRMI BRPL BRGE BRLT BRHS BRHC BRTS BRTC BRVS BRVC BRIE BRID Rd,Rr Rd,Rr Rd,Rr Rd,K Rr, b Rr, b A, b A, b s, k s, k k k k k k k k k k k k k k k k k k k Operands k Description call Subroutine Subroutine Return Interrupt Return Compare, Skip if Equal Compare Compare with Carry Compare with Immediate Skip if Bit in Register Cleared Skip if Bit in Register Set Skip if Bit in I/O Register Cleared Skip if Bit in I/O Register Set Branch if Status Flag Set Branch if Status Flag Cleared Branch if Equal Branch if Not Equal Branch if Carry Set Branch if Carry Cleared Branch if Same or Higher Branch if Lower Branch if Minus Branch if Plus Branch if Greater or Equal, Signed Branch if Less Than, Signed Branch if Half Carry Flag Set Branch if Half Carry Flag Cleared Branch if T Flag Set Branch if T Flag Cleared Branch if Overflow Flag is Set Branch if Overflow Flag is Cleared Branch if Interrupt Enabled Branch if Interrupt Disabled Operation PC PC PC if (Rd = Rr) PC Rd - Rr Rd - Rr - C Rd - K if (Rr(b) = 0) PC if (Rr(b) = 1) PC if (I/O(A,b) = 0) PC If (I/O(A,b) =1) PC if (SREG(s) = 1) then PC if (SREG(s) = 0) then PC if (Z = 1) then PC if (Z = 0) then PC if (C = 1) then PC if (C = 0) then PC if (C = 0) then PC if (C = 1) then PC if (N = 1) then PC if (N = 0) then PC if (N V= 0) then PC if (N V= 1) then PC if (H = 1) then PC if (H = 0) then PC if (T = 1) then PC if (T = 0) then PC if (V = 1) then PC if (V = 0) then PC if (I = 1) then PC if (I = 0) then PC Data Transfer Instructions MOV MOVW LDI LDS LD LD LD LD LD Rd, Rr Rd, Rr Rd, K Rd, k Rd, X Rd, X+ Rd, -X Rd, Y Rd, Y+ Copy Register Copy Register Pair Load Immediate Load Direct from data space Load Indirect Load Indirect and Post-Increment Load Indirect and Pre-Decrement Load Indirect Load Indirect and Post-Increment Rd Rd+1:Rd Rd Rd Rd Rd X X X - 1, Rd (X) Rd (Y) Rd Y Rr Rr+1:Rr K (k) (X) (X) X+1 X-1 (X) (Y) (Y) Y+1 None None None None None None None None None 1 1 1 2(1)(2) 1(1)(2) 1(1)(2) 2(1)(2) 1(1)(2) 1(1)(2) PC + 2 or 3 PC + 2 or 3 PC + 2 or 3 PC + 2 or 3 PC + k + 1 PC + k + 1 PC + k + 1 PC + k + 1 PC + k + 1 PC + k + 1 PC + k + 1 PC + k + 1 PC + k + 1 PC + k + 1 PC + k + 1 PC + k + 1 PC + k + 1 PC + k + 1 PC + k + 1 PC + k + 1 PC + k + 1 PC + k + 1 PC + k + 1 PC + k + 1 k STACK STACK PC + 2 or 3 Flags None None I None Z,C,N,V,S,H Z,C,N,V,S,H Z,C,N,V,S,H None None None None None None None None None None None None None None None None None None None None None None None None #Clocks 3 / 4(1) 4 / 5(1) 4 / 5(1) 1/2/3 1 1 1 1/2/3 1/2/3 2/3/4 2/3/4 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2
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Mnemonics LD LDD LD LD LD LDD STS ST ST ST ST ST ST STD ST ST ST STD LPM LPM LPM ELPM ELPM ELPM SPM SPM IN OUT PUSH POP Z+ Rd, A A, Rr Rr Rd Rd, Z Rd, Z+ Rd, Z Rd, Z+ Operands Rd, -Y Rd, Y+q Rd, Z Rd, Z+ Rd, -Z Rd, Z+q k, Rr X, Rr X+, Rr -X, Rr Y, Rr Y+, Rr -Y, Rr Y+q, Rr Z, Rr Z+, Rr -Z, Rr Z+q,Rr Description Load Indirect and Pre-Decrement Load Indirect with Displacement Load Indirect Load Indirect and Post-Increment Load Indirect and Pre-Decrement Load Indirect with Displacement Store Direct to Data Space Store Indirect Store Indirect and Post-Increment Store Indirect and Pre-Decrement Store Indirect Store Indirect and Post-Increment Store Indirect and Pre-Decrement Store Indirect with Displacement Store Indirect Store Indirect and Post-Increment Store Indirect and Pre-Decrement Store Indirect with Displacement Load Program Memory Load Program Memory Load Program Memory and Post-Increment Extended Load Program Memory Extended Load Program Memory Extended Load Program Memory and PostIncrement Store Program Memory Store Program Memory and Post-Increment by 2 In From I/O Location Out To I/O Location Push Register on Stack Pop Register from Stack Bit and Bit-test Instructions LSL Rd Logical Shift Left Rd(n+1) Rd(0) C Rd(n) Rd(7) C Rd(n), 0, Rd(7) Rd(n+1), 0, Rd(0) Z,C,N,V,H 1 Operation Y Rd Rd Rd Rd Z Z Rd Rd (k) (X) (X) X X (X) (Y) (Y) Y Y (Y) (Y + q) (Z) (Z) Z Z (Z + q) R0 Rd Rd Z R0 Rd Rd Z (RAMPZ:Z) (RAMPZ:Z) Z Rd I/O(A) STACK Rd Y-1 (Y) (Y + q) (Z) (Z), Z+1 Z - 1, (Z) (Z + q) Rd Rr Rr, X+1 X - 1, Rr Rr Rr, Y+1 Y - 1, Rr Rr Rr Rr Z+1 Z-1 Rr (Z) (Z) (Z), Z+1 (RAMPZ:Z) (RAMPZ:Z) (RAMPZ:Z), Z+1 R1:R0 R1:R0, Z+2 I/O(A) Rr Rr STACK Flags None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None #Clocks 2(1)(2) 2(1)(2) 1(1)(2) 1(1)(2) 2(1)(2) 2(1)(2) 2(1) 1(1) 1(1) 2(1) 1(1) 1(1) 2(1) 2(1) 1(1) 1(1) 2(1) 2(1) 3 3 3 3 3 3 1 1 1(1) 2(1)
LSR
Rd
Logical Shift Right
Z,C,N,V
1
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Mnemonics ROL Operands Rd Description Rotate Left Through Carry Operation Rd(0) Rd(n+1) C Rd(7) Rd(n) C Rd(n) Rd(3..0) SREG(s) SREG(s) I/O(A, b) I/O(A, b) T Rd(b) C C N N Z Z I I S S V V T T H H MCU Control Instructions BREAK NOP SLEEP WDR Break No Operation Sleep Watchdog Reset (see specific descr. for Sleep) (see specific descr. for WDR) (See specific descr. for BREAK) None None None None 1 1 1 1 C, Rd(n), Rd(7) C, Rd(n+1), Rd(0) Rd(n+1), n=0..6 Rd(7..4) 1 0 1 0 Rr(b) T 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Flags Z,C,N,V,H #Clocks 1
ROR
Rd
Rotate Right Through Carry
Z,C,N,V
1
ASR SWAP BSET BCLR SBI CBI BST BLD SEC CLC SEN CLN SEZ CLZ SEI CLI SES CLS SEV CLV SET CLT SEH CLH
Rd Rd s s A, b A, b Rr, b Rd, b
Arithmetic Shift Right Swap Nibbles Flag Set Flag Clear Set Bit in I/O Register Clear Bit in I/O Register Bit Store from Register to T Bit load from T to Register Set Carry Clear Carry Set Negative Flag Clear Negative Flag Set Zero Flag Clear Zero Flag Global Interrupt Enable Global Interrupt Disable Set Signed Test Flag Clear Signed Test Flag Set Two's Complement Overflow Clear Two's Complement Overflow Set T in SREG Clear T in SREG Set Half Carry Flag in SREG Clear Half Carry Flag in SREG
Z,C,N,V None SREG(s) SREG(s) None None T None C C N N Z Z I I S S V V T T H H
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Notes:
1. Cycle times for Data memory accesses assume internal memory accesses, and are not valid for accesses via the external RAM interface. 2. One extra cycle must be added when accessing Internal SRAM.
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33. Packaging information
33.1 64A
PIN 1 B
PIN 1 IDENTIFIER
e
E1
E
D1 D C
0~7 A1 L
COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL A A1 A2 D D1 E MIN - 0.05 0.95 15.75 13.90 15.75 13.90 0.30 0.09 0.45 NOM - - 1.00 16.00 14.00 16.00 14.00 - - - 0.80 TYP MAX 1.20 0.15 1.05 16.25 14.10 16.25 14.10 0.45 0.20 0.75 Note 2 Note 2 NOTE
A2
A
Notes: 1.This package conforms to JEDEC reference MS-026, Variation AEB. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.10 mm maximum.
E1 B C L e
10/5/2001 2325 Orchard Parkway San Jose, CA 95131 TITLE 64A, 64-lead, 14 x 14 mm Body Size, 1.0 mm Body Thickness, 0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP) DRAWING NO. 64A REV. B
R
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33.2 64M2
D
Marked Pin# 1 ID
E
C
TOP VIEW
SEATING PLANE
A1 A
K L D2
Pin #1 Corner
0.08 C
SIDE VIEW
1 2 3
Option A
Pin #1 Triangle
COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL
Option B
Pin #1 Chamfer (C 0.30)
E2
MIN 0.80 - 0.18 8.90 7.50 8.90 7.50
NOM 0.90 0.02 0.25 9.00 7.65 9.00 7.65 0.50 BSC
MAX 1.00 0.05 0.30 9.10 7.80 9.10 7.80
NOTE
A A1 b D
K b e
Option C
D2
Pin #1 Notch (0.20 R)
E E2 e L K
BOTTOM VIEW
0.35 0.20
0.40 0.27
0.45 0.40
Note: 1. JEDEC Standard MO-220, (SAW Singulation) Fig. 1, VMMD. 2. Dimension and tolerance conform to ASMEY14.5M-1994.
5/25/06 2325 Orchard Parkway San Jose, CA 95131 TITLE 64M2, 64-pad, 9 x 9 x 1.0 mm Body, Lead Pitch 0.50 mm, 7.65 mm Exposed Pad, Micro Lead Frame Package (MLF) DRAWING NO. 64M2 REV. D
R
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34. Electrical Characteristics
34.1 Absolute Maximum Ratings*
*NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Operating Temperature.................................. -55C to +125C Storage Temperature ..................................... -65C to +150C Voltage on any Pin with respect to Ground..-0.5V to VCC+0.5V Maximum Operating Voltage ............................................ 3.6V DC Current per I/O Pin ............................................... 20.0 mA DC Current VCC and GND Pins................................ 200.0 mA
34.2
DC Characteristics
Current Consumption
Parameter Condition 32 kHz, Ext. Clk VCC = 1.8V VCC = 3.0V 1 MHz, Ext. Clk Active 2 MHz, Ext. Clk 32 MHz, Ext. Clk 32 kHz, Ext. Clk VCC = 1.8V VCC = 3.0V VCC = 1.8V VCC = 3.0V Power Supply Current(1) VCC = 3.0V VCC = 1.8V VCC = 3.0V 1 MHz, Ext. Clk Idle VCC = 1.8V VCC = 3.0V 2 MHz, Ext. Clk 32 MHz, Ext. Clk All Functions Disabled All Functions Disabled, T = 85C Power-down mode ULP, WDT, Sampled BOD ULP, WDT, Sampled BOD, T=85C RTC 1 kHz from Low Power 32 kHz TOSC RTC from Low Power 32 kHz TOSC Reset Current Consumption without Reset pull-up resistor current VCC = 1.8V VCC = 3.0V VCC = 3.0V VCC = 3.0V VCC = 3.0V VCC = 1.8V VCC = 3.0V VCC = 3.0V VCC = 1.8V VCC = 3.0V VCC = 3.0V VCC = 3.0V Min Typ 25 71 317 A 697 613 1340 15.7 3.6 6.9 112 A 215 224 430 6.9 0.1 1.75 1 1 2.7 0.55 0.65 1.16 1300 10 A 5 350 650 8 mA 800 1800 18 mA Max Units
Table 34-1.
Symbol
ICC
Power-save mode
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Table 34-1.
Symbol
Current Consumption
Parameter
(2)
Condition
Min
Typ
Max
Units
Module current consumption RC32M RC32M w/DFLL RC2M RC2M w/DFLL RC32K PLL
460 Internal 32.768 kHz oscillator as DFLL source 594 101 Internal 32.768 kHz oscillator as DFLL source 134 27 Multiplication factor = 10x 202 1 128 1 80 74 No prescaling No prescaling 250 kS/s - Int. 1V Ref 1000 kS/s, Single channel, Int. 1V Ref 1000 KS/s, Single channel, Int. 1V Ref Int.1.1V Ref, Refresh 16CLK Int. 1.1V Ref, Refresh 16CLK 27 1 2.9 1.8 0.95 2.9 1.1 195 103 Rx and Tx enabled, 9600 BAUD 5.4 A 128 Prescaler DIV1 20 223 mA A
Watchdog normal mode BOD Continuous mode BOD Sampled mode Internal 1.00 V ref Temperature reference RTC with int. 32 kHz RC as source RTC with ULP as source ADC DAC Normal Mode DAC Low-Power Mode DAC S/H Normal Mode DAC Low-Power Mode S/H AC High-speed AC Low-power USART DMA Timer/Counter AES
ICC
Note:
1. All Power Reduction Registers set. Typical numbers measured at T = 25C if nothing else is specified. 2. All parameters measured as the difference in current consumption between module enabled and disabled. All data at VCC = 3.0V, ClkSYS = 1 MHz External clock with no prescaling, T = 25C.
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34.3 Operating Voltage and Frequency
Table 34-2.
Symbol
Operating voltage and voltage and frequency
Parameter Condition VCC = 1.6V Min 0 0 0 0 Typ Max 12 12 MHz 32 32 Units
ClkSYS
System clock frequency
VCC = 1.8V VCC = 2.7V VCC = 3.6V
The maximum System clock frequency of the XMEGA A3 devices is depending on VCC. As shown in Figure 34-1 on page 63 the Frequency vs. V C C curve is linear between 1.8V < VCC < 2.7V. Figure 34-1. Maximum Frequency vs. Vcc
MHz
32
Safe Operating Area
12
1.6 1.8
2.7
3.6
V
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34.4 Flash and EEPROM Memory Characteristics
Endurance and Data Retention
Parameter Condition 25C Write/Erase cycles 85C Flash 25C Data retention 55C 25C Write/Erase cycles 85C EEPROM 25C Data retention 55C 25 100 Year 30K 25 80K Cycle 100 Year 10K Min 10K Cycle Typ Max Units
Table 34-3.
Symbol
Table 34-4.
Symbol
Programming time
Parameter Chip Erase Flash, EEPROM Page Erase Flash Page Write Page WriteAutomatic Page Erase and Write Page Erase EEPROM Page Write Page WriteAutomatic Page Erase and Write Condition
(2)
Min
Typ(1) 40 6 6 12 6 6 12
Max
Units
and SRAM Erase
ms
Notes:
1. Programming is timed from the internal 2 MHz oscillator. 2. EEPROM is not erased if the EESAVE fuse is programmed.
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34.5 ADC Characteristics
ADC Characteristics
Parameter Resolution Integral Non-Linearity Differential Non-Linearity Gain Error Offset Error ADCclk ADC Clock frequency Conversion rate Conversion time (propagation delay) Sampling Time Conversion range VREF Reference voltage Input bandwidth INT1V INTVCC
SCALEDVCC
Table 34-5.
Symbol RES INL DNL
Condition Programmable: 8/12 500 ksps 500 ksps
Min 8 -5
Typ 12
Max 12 5
Units Bits LSB LSB mV mV
< 1 < 10 < 2
Max is 1/4 of Peripheral Clock
2000 2000
kHz ksps ADCclk cycles uS
(RES+2)/2+GAIN RES = 8 or 12, GAIN = 0 or 1 1/2 ADCclk cycle
5 0.25 0 1.0
7
8
VREF Vcc-0.6V
V V kHz
Internal 1.00V reference Internal VCC/1.6 Scaled internal VCC/10 input Reference input resistance Start-up time Internal input sampling speed
Temp. sensor, VCC/10, Bandgap
1.00 VCC/1.6 VCC/10 > 10
V V V M s 100 ksps
RAREF
Table 34-6.
Symbol
ADC Gain Stage Characteristics
Parameter Gain error Offset error VREF = Int. 1V Condition 1 to 64 gain Min Typ < 1 < 1 0.12 0.06 1000 kHz mV 64x gain VREF = Ext. 2V Clock rate Same as ADC Max Units %
Vrms
Noise level at input
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34.6 DAC Characteristics
DAC Characteristics
Parameter Integral Non-Linearity Differential Non-Linearity Conversion rate External reference voltage Reference input impedance DC output impedance Max output voltage Min output voltage
Offset factory calibration accuracy Gain factory calibration accuracy
Table 34-7.
Symbol INL DNL Fclk AREF
Condition VCC = 1.6-3.6V VCC = 1.6-3.6V VREF = Ext. ref VREF = Ext. ref VREF= AVCC
Min
Typ 5 <1
Max
Units
LSB
1000 1.1 >10 AVCC-0.6
ksps V M k
Rload=100k Rload=100k Continues mode, VCC=3.0V, VREF = Int 1.00V, T=85C
AVCC*0.98
V
0.015 0.5 LSB 2.5
34.7
Analog Comparator Characteristics
Analog Comparator Characteristics
Parameter Input Offset Voltage Input Leakage Current Hysteresis, No Hysteresis, Small Hysteresis, Large Condition VCC = 1.6 - 3.6V VCC = 1.6 - 3.6V VCC = 1.6 - 3.6V VCC = 1.6 - 3.6V VCC = 1.6 - 3.6V VCC = 3.0V, T= 85C mode = HS mode = HS mode = HS mode = HS mode = LP 110 175 Min Typ <10 < 1000 0 20 mV 40 100 ns Max Units mV pA mV
Table 34-8.
Symbol Voff Ilk Vhys1 Vhys2 Vhys3
tdelay
Propagation delay
VCC = 1.6 - 3.6V VCC = 1.6 - 3.6V
34.8
Bandgap Characteristics
Bandgap Voltage Characteristics
Parameter Bandgap startup time As input to AC or ADC Bandgap voltage T= 85C, After calibration ADC/DAC ref 1 Variation over voltage and temperature VCC = 1.6 - 3.6V, T = -40C to 85C 5 % 0.99 1.5 1.1 1 1.01 V Condition As reference for ADC or DAC Min Typ Max Units s
Table 34-9.
Symbol
1 Clk_PER + 2.5s
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34.9 Brownout Detection Characteristics
Table 34-10. Brownout Detection Characteristics(1)
Symbol Parameter BOD level 0 falling Vcc BOD level 1 falling Vcc BOD level 2 falling Vcc BOD level 3 falling Vcc BOD level 4 falling Vcc BOD level 5 falling Vcc BOD level 6 falling Vcc BOD level 7 falling Vcc Hysteresis Note: BOD level 0-5 Condition Min Typ 1.62 1.9 2.17 2.43 V 2.68 2.96 3.22 3.49 1 % Max Units
1. BOD is calibrated on BOD level 0 at 85C.
34.10 PAD Characteristics
Table 34-11. PAD Characteristics
Symbol VIH Parameter Input High Voltage Condition VCC = 2.4 - 3.6V VCC = 1.6 - 2.4V Input Low Voltage VCC = 2.4 - 3.6V VCC = 1.6 - 2.4V IOH = 15 mA, VCC = 3.3V VOL Output Low Voltage GPIO IOH = 10 mA, VCC = 3.0V IOH = 5 mA, VCC = 1.8V IOH = -8 mA, VCC = 3.3V VOH Output High Voltage GPIO IOH = -6 mA, VCC = 3.0V IOH = -2 mA, VCC = 1.8V IIL IIH RP RRST Input Leakage Current I/O pin Input Leakage Current I/O pin I/O pin Pull/Buss keeper Resistor Reset pin Pull-up Resistor Input hysteresis 2.6 2.1 1.4 Min 0.7*VCC 0.8*VCC -0.5 -0.5 0.4 0.3 0.2 2.9 2.7 1.6 <0.001 <0.001 20 k 20 0.5 V 1 A 1 Typ Max VCC+0.5 VCC+0.5 0.3*VCC 0.2*VCC 0.76 V 0.64 0.46 Units
VIL
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34.11 POR Characteristics
Table 34-12. Power-on Reset Characteristics
Symbol VPOTVPOT+ Parameter POR threshold voltage falling Vcc POR threshold voltage rising Vcc Condition Min Typ 1 V 1.45 Max Units
34.12 Reset Characteristics
Table 34-13. Reset Characteristics
Symbol Parameter Minimum reset pulse width Reset threshold voltage VCC = 2.7 - 3.6V VCC = 1.6 - 2.7V Condition Min Typ 90 0.45*VCC 0.42*VCC Max Units ns V
34.13 Oscillator Characteristics
Table 34-14. Internal 32.768 kHz Oscillator Characteristics
Symbol Parameter Accuracy Condition T = 85C, VCC = 3V, After production calibration Min -0.5 Typ Max 0.5 Units %
Table 34-15. Internal 2 MHz Oscillator Characteristics
Symbol Parameter Accuracy DFLL Calibration step size Condition T = 85C, VCC = 3V, After production calibration T = 25C, VCC = 3V Min -1.5 0.15 Typ Max 1.5 % Units
Table 34-16. Internal 32 MHz Oscillator Characteristics
Symbol Parameter Accuracy DFLL Calibration stepsize Condition T = 85C, VCC = 3V, After production calibration T = 25C, VCC = 3V Min -1.5 0.2 Typ Max 1.5 % Units
Table 34-17. Internal 32 kHz, ULP Oscillator Characteristics
Symbol Parameter Output frequency 32 kHz ULP OSC Condition T = 85C, VCC = 3.0V Min Typ 26 Max Units kHz
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35. Typical Characteristics
35.1 Active Supply Current
Figure 35-1. Active Supply Current vs. Frequency
fSYS = 0 - 1.0 MHz External clock, T = 25C
900 800 700 600 ICC [uA] 500 400 300 200 100 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency [MHz]
3.3 V 3.0 V 2.7 V 2.2 V 1.8 V
Figure 35-2. Active Supply Current vs. Frequency
fSYS = 1 - 32 MHz External clock, T = 25C
20 18 16 14 ICC [mA] 12 10 8 6 4 2 0 0 4 8 12 16 Frequency [MHz] 20 24 28 32
3.3 V 3.0 V 2.7 V
2.2 V 1.8 V
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Figure 35-3. Active Supply Current vs. Vcc
fSYS = 1.0 MHz External Clock
1000 900 800 700 ICC [uA] 600 500 400 300 200 100 0 1.6 1.8 2 2.2 2.4 2.6 VCC [V] 2.8 3 3.2 3.4
85 C 25 C -40 C
3.6
Figure 35-4. Active Supply Current vs. VCC
fSYS = 32.768 kHz internal RC
140 120 100 ICC [uA] 80 60 40 20 0 1.6 1.8 2 2.2 2.4 2.6 VCC [V] 2.8 3 3.2 3.4
-40 C 25 C 85 C
3.6
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Figure 35-5. Active Supply Current vs. Vcc
fSYS = 2.0 MHz internal RC
2000 1800 1600 1400 ICC [uA] 1200 1000 800 600 400 200 0 1.6 1.8 2 2.2 2.4 2.6 VCC [V] 2.8 3 3.2 3.4
-40 C 25 C 85 C
3.6
Figure 35-6. Active Supply Current vs. Vcc
fSYS = 32 MHz internal RC prescaled to 8 MHz
3.5 3.0 2.5 ICC [mA] 2.0 1.5 1.0 0.5 0 1.6 1.8 2 2.2 2.4 2.6 VCC [V] 2.8 3 3.2 3.4
-40 C 25 C 85 C
3.6
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Figure 35-7. Active Supply Current vs. Vcc
fSYS = 32 MHz internal RC
25
20
-40 C 25 C 85 C
ICC [mA]
15
10
5
0 2.7 2.8 2.9 3 3.1 3.2 3.3 3.4 3.5 3.6 VCC [V]
35.2
Idle Supply Current
Figure 35-8. Idle Supply Current vs. Frequency
fSYS = 0 - 1.0 MHz, T = 25C
250
3.3 V 3.0 V
200
2.7 V
ICC [uA] 150
2.2 V 1.8 V
100
50
0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency [MHz]
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Figure 35-9. Idle Supply Current vs. Frequency
fSYS = 1 - 32 MHz, T = 25C
8 7 6 5 ICC [mA] 4 3 2 1 0 0 4 8 12 16 Frequency [MHz] 20 24 28
3.3 V 3.0 V 2.7 V
2.2 V 1.8 V
32
Figure 35-10. Idle Supply Current vs. Vcc
fSYS = 1.0 MHz External Clock
300
250
85 C 25 C -40 C
200 ICC [uA]
150
100
50
0 1.6 1.8 2 2.2 2.4 2.6 VCC [V] 2.8 3 3.2 3.4 3.6
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Figure 35-11. Idle Supply Current vs. Vcc
fSYS = 32.768 kHz internal RC
40 35 30 25 ICC [uA] 20 15 10 5 0 1.6 1.8 2 2.2 2.4 2.6 VCC [V] 2.8 3 3.2 3.4
85 C -40 C 25 C
3.6
Figure 35-12. Idle Supply Current vs. Vcc
fSYS = 2.0 MHz internal RC
700 600 500 ICC [uA] 400 300 200 100 0 1.6 1.8 2 2.2 2.4 2.6 VCC [V] 2.8 3 3.2 3.4
-40 C 25 C 85 C
3.6
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Figure 35-13. Idle Supply Current vs. Vcc
fSYS = 32 MHz internal RC prescaled to 8 MHz
3.5 3.0 2.5 ICC [mA] 2.0 1.5 1.0 0.5 0 1.6 1.8 2 2.2 2.4 2.6 VCC [V] 2.8 3 3.2 3.4
-40 C 25 C 85 C
3.6
Figure 35-14. Idle Supply Current vs. Vcc
fSYS = 32 MHz internal RC
10
-40 C 25 C 85 C
8
ICC [mA]
6
4
2
0 2.7 2.8 2.9 3 3.1 3.2 3.3 3.4 3.5 3.6 VCC [V]
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35.3 Power-down Supply Current
Figure 35-15. Power-down Supply Current vs. Temperature
2 1.8 1.6 1.4 ICC [uA] 1.2 1 0.8 0.6 0.4 0.2 0 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Temperature [C]
3.3 V 3.0 V 2.7 V 2.2 V 1.8 V
Figure 35-16. Power-down Supply Current vs. Temperature
With WDT and sampled BOD enabled.
3
2.5
3.3 V 3.0 V 2.7 V 2.2 V 1.8 V
2 ICC [uA]
1.5
1
0.5
0 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Temperature [C]
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35.4 Power-save Supply Current
Figure 35-17. Power-save Supply Current vs. Temperature
With WDT, sampled BOD and RTC from ULP enabled
3
2.5
3.3 V 3.0 V 2.7 V 1.8 V 2.2 V
2 ICC [uA]
1.5
1
0.5
0 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Temperature [C]
35.5
Pin Pull-up
Figure 35-18. Reset Pull-up Resistor Current vs. Reset Pin Voltage
VCC = 1.8V
100
80
IRESET [uA]
60
40
20
0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 VRESET [V]
-40 C 25 C 85 C
1.8
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Figure 35-19. Reset Pull-up Resistor Current vs. Reset Pin Voltage
VCC = 3.0V
160 140 120 IRESET [uA] 100 80 60 40 20 0 0 0.5 1 1.5 VRESET [V] 2 2.5 3
-40 C 25 C 85 C
Figure 35-20. Reset Pull-up Resistor Current vs. Reset Pin Voltage
VCC = 3.3V
180 160 140 120 IRESET [uA] 100 80 60 40 20 0 0 0.5 1 1.5 VRESET [V] 2 2.5 3
-40 C 25 C 85 C
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35.6 Pin Output Voltage vs. Sink/Source Current
Figure 35-21. I/O Pin Output Voltage vs. Source Current
Vcc = 1.8V
2 1.8 1.6 1.4 VPIN [V] 1.2 1 0.8 0.6 0.4 0.2 0 -12 -10 -8 -6 IPIN [mA] -4 -2 0
-40 C 25 C 85 C
Figure 35-22. I/O Pin Output Voltage vs. Source Current
Vcc = 3.0V
3.5 3 2.5 VPIN [V] 2 1.5 1 0.5 0 -20 -18 -16 -14 -12 -10 IPIN [mA] -8 -6 -4 -2 0
-40 C 25 C 85 C
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Figure 35-23. I/O Pin Output Voltage vs. Source Current
Vcc = 3.3V
3.5 3 2.5 VPIN [V] 2 1.5 1 0.5 0 -20 -18 -16 -14 -12 -10 IPIN [mA] -8 -6 -4 -2 0
-40 C 25 C 85 C
Figure 35-24. I/O Pin Output Voltage vs. Sink Current
Vcc = 1.8V
1.8 1.6 1.4 1.2 VPIN [V] 1 0.8 0.6 0.4 0.2 0 0 2 4 6 8 10 IPIN [mA] 12 14
85C 25C
-40 C
16
18
20
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Figure 35-25. I/O Pin Output Voltage vs. Sink Current
Vcc = 3.0V
0.7
85 C
0.6 0.5 VPIN [V] 0.4 0.3 0.2 0.1 0 0 2 4 6 8 10 IPIN [mA] 12 14 16 18 20
25 C -40 C
Figure 35-26. I/O Pin Output Voltage vs. Sink Current
Vcc = 3.3V
0.7 0.6 0.5 VPIN [V] 0.4 0.3 0.2 0.1 0 0 2 4 6 8 10 IPIN [mA] 12 14 16 18 20
85 C 25 C -40 C
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35.7 Pin Thresholds and Hysteresis
Figure 35-27. I/O Pin Input Threshold Voltage vs. VCC
VIH - I/O Pin Read as "1"
2.5
2
-40 C 25 C 85 C
Vthreshold [V]
1.5
1
0.5
0 1.6 1.8 2 2.2 2.4 2.6 VCC [V] 2.8 3 3.2 3.4 3.6
Figure 35-28. I/O Pin Input Threshold Voltage vs. VCC
VIL - I/O Pin Read as "0"
1.8 1.6 1.4 1.2 Vthreshold [V] 1 0.8 0.6 0.4 0.2 0 1.6 1.8 2 2.2 2.4 2.6 VCC [V] 2.8 3 3.2 3.4
85 C 25 C -40 C
3.6
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Figure 35-29. I/O Pin Input Hysteresis vs. VCC
0.7 0.6 0.5 Vthreshold [V] 0.4 0.3 0.2 0.1 0 1.6 1.8 2 2.2 2.4 2.6 VCC [V] 2.8 3 3.2 3.4 3.6
85 C 25 C -40 C
Figure 35-30. Reset Input Threshold Voltage vs. VCC
VIH - I/O Pin Read as "1"
1.8 1.6 1.4 VTHRESHOLD [V] 1.2 1 0.8 0.6 0.4 0.2 0 1.6 1.8 2 2.2 2.4 2.6 VCC [V] 2.8 3 3.2 3.4
-40 C 25 C 85 C
3.6
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Figure 35-31. Reset Input Threshold Voltage vs. VCC
VIL - I/O Pin Read as "0"
1.8 1.6 1.4 VTHRESHOLD [V] 1.2 1 0.8 0.6 0.4 0.2 0 1.6 1.8 2 2.2 2.4 2.6 VCC [V] 2.8 3 3.2 3.4
-40 C 25 C 85 C
3.6
35.8
Bod Thresholds
Figure 35-32. BOD Thresholds vs. Temperature
BOD Level = 1.6V
1.67
1.66
Rising Vcc Falling Vcc
1.65 VBOT [V]
1.64
1.63
1.62
1.61 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Temperature [C]
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Figure 35-33. BOD Thresholds vs. Temperature
BOD Level = 2.9V
3.06 3.04 3.02 3 VBOT [V] 2.98
Rising Vcc
Falling Vcc
2.96 2.94 2.92 2.9 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Temperature [C]
35.9
35.9.1
Internal Oscillator Speed
Internal 32.768 kHz Oscillator Figure 35-34. Internal 32.768 kHz Oscillator Calibration Step Size
T = -40 to 85C, VCC = 3V
0.80 %
0.65 % Step size: f [kHz]
0.50 %
0.35 %
0.20 %
0.05 % 0 32 64 96 128 RC32KCAL[7..0] 160 192 224 256
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35.9.2 Internal 2 MHz Oscillator Figure 35-35. Internal 2 MHz Oscillator CALA Calibration Step Size
T = -40 to 85C, VCC = 3V
0.50 % 0.40 % 0.30 % Step size: f [MHz] 0.20 % 0.10 % 0.00 % -0.10 % -0.20 % -0.30 % 0 16 32 48 64 80 96 112 128 DFLLRC2MCALA
Figure 35-36. Internal 2 MHz Oscillator CALB Calibration Step Size
T = -40 to 85C, VCC = 3V
3.00 %
2.50 %
Step size: f [MHz]
2.00 %
1.50 %
1.00 %
0.50 %
0.00 % 0 8 16 24 32 DFLLRC2MCALB 40 48 56 64
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35.9.3 Internal 32 MHZ Oscillator Figure 35-37. Internal 32 MHz Oscillator CALA Calibration Step Size
T = -40 to 85C, VCC = 3V
0.60 % 0.50 % 0.40 % Step size: f [MHz] 0.30 % 0.20 % 0.10 % 0.00 % -0.10 % -0.20 % 0 16 32 48 64 80 96 112 128 DFLLRC32MCALA
Figure 35-38. Internal 32 MHz Oscillator CALB Calibration Step Size
T = -40 to 85C, VCC = 3V
3.00 %
2.50 %
Step size: f [MHz]
2.00 %
1.50 %
1.00 %
0.50 %
0.00 % 0 8 16 24 32 40 48 56 64 DFLLRC32MCALB
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35.10 Module current consumption
Figure 35-39. AC current consumption vs. Vcc
Low-power Mode
120
85 C 25 C -40 C
Module current consumption [uA]
100
80
60
40
20
0 1.6 1.8 2 2.2 2.4 2.6 VCC [V] 2.8 3 3.2 3.4 3.6
Figure 35-40. Power-up current consumption vs. Vcc
700 600 500 ICC [uA] 400 300 200 100 0 0.4 0.6 0.8 1 VCC [V] 1.2 1.4 1.6
-40 C 25 C 85 C
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35.11 Reset Pulsewidth
Figure 35-41. Minimum Reset Pulse Width vs. Vcc
120
100
80 tRST [ns]
85 C 25 C -40 C
60
40
20
0 1.6 1.8 2 2.2 2.4 2.6 VCC [V] 2.8 3 3.2 3.4 3.6
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36. Errata
36.1
36.1.1
ATxmega256A3
rev. B * * * * * * * * * *
Bandgap voltage input for the ACs cannot be changed when used for both ACs simultaneously ADC gain stage output range is limited to 2.4V Sampled BOD in Active mode will cause noise when bandgap is used as reference Bandgap measurement with the ADC is non-functional when VCC is below 2.7V BOD will be enabled after any reset
Writing EEPROM or Flash while reading any of them will not work
ADC has increased INL error for some operating conditions DAC has increased INL or noise for some operating conditions VCC voltage scaler for AC is non-linear Maximum operating frequency below 1.76V is 8 MHz
1. Bandgap voltage input for the ACs cannot be changed when used for both ACs simultaneously If the bandgap voltage is selected as input for one Analog Comparator (AC) and then selected/deselected as input for the another AC, the first comparator will be affected for up to 1 us and could potentially give a wrong comparison result. Problem fix/Workaround If the Bandgap is required for both ACs simultaneously, configure the input selection for both ACs before enabling any of them. 2. ADC gain stage output range is limited to 2.4 V The amplified output of the ADC gain stage will never go above 2.4 V, hence the differential input will only give correct output when below 2.4 V/gain. For the available gain settings, this gives a differential input range of:
- - - - - - - 1x 2x 4x 8x 16x 32x 64x gain: gain: gain: gain: gain: gain: gain: 2.4 1.2 0.6 300 150 75 38 V V V mV mV mV mV
Problem fix/Workaround Keep the amplified voltage output from the ADC gain stage below 2.4 V in order to get a correct result, or keep ADC voltage reference below 2.4 V. 3. Sampled BOD in Active mode will cause noise when bandgap is used as reference Using the BOD in sampled mode when the device is running in Active or Idle mode will add noise on the bandgap reference for ADC, DAC and Analog Comparator.
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Problem fix/Workaround If the bandgap is used as reference for either the ADC, DAC and Analog Comparator, the BOD must not be set in sampled mode. 4. Bandgap measurement with the ADC is non-functional when VCC is below 2.7V The ADC cannot be used to do bandgap measurements when VCC is below 2.7V. Problem fix/Workaround If internal voltages must be measured when VCC is below 2.7V, measure the internal 1.00V reference instead of the bandgap. 5. BOD will be enabled after any reset If any reset source goes active, the BOD will be enabled and keep the device in reset if the VCC voltage is below the programmed BOD level. During Power-On Reset, reset will not be released until VCC is above the programmed BOD level even if the BOD is disabled. Problem fix/Workaround Do not set the BOD level higher than VCC even if the BOD is not used. 6. Writing EEPROM or Flash while reading any of them will not work The EEPROM and Flash cannot be written while reading EEPROM or Flash, or while executing code in Active mode. Problem fix/Workaround Enter IDLE sleep mode within 2.5 uS (Five 2 MHz clock cycles and 80 32 MHz clock cycles) after starting an EEPROM or flash write operation. Wake-up source must either be EEPROM ready or NVM ready interrupt. Alternatively set up a Timer/Counter to give an overflow interrupt 7 mS after the erase or write operation has started, or 13 mS after atomic erase-and-write operation has started, and then enter IDLE sleep mode. 7. ADC has increased INL error for some operating conditions Some ADC configurations or operating condition will result in increased INL error. In differential mode INL is increased to: - 6 LSB for sample rates above 1 Msps, and up to 8 LSB for 2 Msps sample rate. - 6 LSB for reference voltage below 1.1V when VCC is above 3.0V. - 20 LSB for ambient temperature below 0 degree C and reference voltage below 1.3V. In single ended mode, the INL is increased up to a factor of 3 for the conditions above. Problem fix/Workaround None, avoid using the ADC in the above configurations in order to prevent increased INL error. 8. DAC has increased INL or noise for some operating conditions Some DAC configurations or operating condition will result in increased output error. - INL error is increased up to 35 LSB when VCC < 2.0V - Enabling Sample and Hold, will increase noise and reduce resolution below 8 bit
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Problem fix/Workaround None, avoid using the DAC in the above configurations in order to prevent increased INL error. 9. VCC voltage scaler for AC is non-linear The 6-bit VCC voltage scaler in the Analog Comparators is non-linear. The typical voltage output versus the scale factor for different VCC voltages is shown below: Figure 36-1. Analog Comparator Voltage Scaler vs. Scalefac
T = 25C
3.5 3
3.3 V 2.7 V
2.5 VSCALE [V] 2 1.5 1 0.5 0 0 5 10 15 20 25 30 35 40 45 50 55 60 65 SCALEFAC
1.8 V
Problem fix/Workaround Use external voltage input for the analog comparator if accurate voltage levels are needed. 10. Maximum operating frequency below 1.76V is 8 MHz To ensure correct operation, the maximum operating frequency below 1.76V VCC is 8 MHz. Problem fix/Workaround None, avoid running the device outside this frequency and voltage limitation.
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36.1.2 rev. A * * * * * * * * * *
Bandgap voltage input for the ACs cannot be changed when used for both ACs simultaneously ADC gain stage output range is limited to 2.4V Sampled BOD in Active mode will cause noise when bandgap is used as reference Flash Power Reduction Mode can not be enabled when entering sleep mode JTAG enable does not override Analog Comparator B output Bandgap measurement with the ADC is non-functional when VCC is below 2.7V DAC refresh may be blocked in S/H mode BOD will be enabled after any reset Both DFLLs and both oscillators has to be enabled for one to work Operating frequnecy and voltage limitations
1. Bandgap voltage input for the ACs cannot be changed when used for both ACs simultaneously If the bandgap voltage is selected as input for one Analog Comparator (AC) and then selected/deselected as input for the another AC, the first comparator will be affected for up to 1 us and could potentially give a wrong comparison result. Problem fix/Workaround If the Bandgap is required for both ACs simultaneously, configure the input selection for both ACs before enabling any of them. 2. ADC gain stage output range is limited to 2.4 V The amplified output of the ADC gain stage will never go above 2.4 V, hence the differential input will only give correct output when below 2.4 V/gain. For the available gain settings, this gives a differential input range of:
- - - - - - - 1x 2x 4x 8x 16x 32x 64x gain: gain: gain: gain: gain: gain: gain: 2.4 1.2 0.6 300 150 75 38 V V V mV mV mV mV
Problem fix/Workaround Keep the amplified voltage output from the ADC gain stage below 2.4 V in order to get a correct result, or keep ADC voltage reference below 2.4 V. 3. Sampled BOD in Active mode will cause noise when bandgap is used as reference Using the BOD in sampled mode when the device is running in Active or Idle mode will add noise on the bandgap reference for ADC, DAC and Analog Comparator. Problem fix/Workaround If the bandgap is used as reference for either the ADC, DAC and Analog Comparator, the BOD must not be set in sampled mode.
93
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4. Flash Power Reduction Mode can not be enabled when entering sleep mode If Flash Power Reduction Mode is enabled when a deep sleep mode, the device will only wake up on every fourth wake-up request. If Flash Power Reduction Mode is enabled when entering Idle sleep mode, the wake-up time will vary with up to 16 CPU clock cycles. Problem fix/Workaround Disable Flash Power Reduction mode before entering sleep mode. 5. JTAG enable does not override Analog Comparator B output When JTAG is enabled this will not override the Anlog Comparator B (ACB)ouput, AC0OUT on pin 7 if this is enabled. Problem fix/Workaround AC0OUT for ACB should not be enabled when JTAG is used. Use only analog comparator output for ACA when JTAG is used, or use the PDI as debug interface. 6. Bandgap measurement with the ADC is non-functional when VCC is below 2.7V The ADC cannot be used to do bandgap measurements when VCC is below 2.7V. Problem fix/Workaround If internal voltages must be measured when VCC is below 2.7V, measure the internal 1.00V reference instead of the bandgap. 7. DAC refresh may be blocked in S/H mode If the DAC is running in Sample and Hold (S/H) mode and conversion for one channel is done at maximum rate (i.e. the DAC is always busy doing conversion for this channel), this will block refresh signals to the second channel. Problem fix/Workarund When using the DAC in S/H mode, ensure that none of the channels is running at maximum conversion rate, or ensure that the conversion rate of both channels is high enough to not require refresh. 8 BOD will be enabled after any reset If any reset source goes active, the BOD will be enabled and keep the device in reset if the VCC voltage is below the programmed BOD level. During Power-On Reset, reset will not be released until VCC is above the programmed BOD level even if the BOD is disabled. Problem fix/Workaround Do not set the BOD level higher than VCC even if the BOD is not used. 9 Both DFLLs and both oscillators has to be enabled for one to work In order to use the automatic runtime calibration for the 2 MHz or the 32MHz internal oscillators, the DFLL for both oscillators and both oscillators has to be enabled for one to work. Problem fix/Workaround Enabled both the DFLLs and both oscillators when using automtics runtime calibartion for one of the internal oscillators.
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10 Operating Frequancy and Voltage Limitation To ensure correct operation, there is a limit on operating frequnecy and voltage. Figure 36-2 on page 95 shows the safe operating area. Figure 36-2. Operating Frequnecy and Voltage Limitation
MHz
30
15
Safe operating area
2.4
3.6
V
Problem fix/Workaround None, avoid using the device outside these frequnecy and voltage limitations.
36.2
36.2.1
ATxmega192A3, ATxmega128A3, ATxmega64A3
rev. B * * * * * * * * * *
Bandgap voltage input for the ACs cannot be changed when used for both ACs simultaneously ADC gain stage output range is limited to 2.4V Sampled BOD in Active mode will cause noise when bandgap is used as reference Bandgap measurement with the ADC is non-functional when VCC is below 2.7V BOD will be enabled after any reset
Writing EEPROM or Flash while reading any of them will not work
ADC has increased INL error for some operating conditions DAC has increased INL or noise for some operating conditions VCC voltage scaler for AC is non-linear Maximum operating frequency below 1.76V is 8 MHz
1. Bandgap voltage input for the ACs cannot be changed when used for both ACs simultaneously If the bandgap voltage is selected as input for one Analog Comparator (AC) and then selected/deselected as input for the another AC, the first comparator will be affected for up to 1 us and could potentially give a wrong comparison result. Problem fix/Workaround If the Bandgap is required for both ACs simultaneously, configure the input selection for both ACs before enabling any of them.
95
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XMEGA A3
2. ADC gain stage output range is limited to 2.4 V The amplified output of the ADC gain stage will never go above 2.4 V, hence the differential input will only give correct output when below 2.4 V/gain. For the available gain settings, this gives a differential input range of:
- - - - - - - 1x 2x 4x 8x 16x 32x 64x gain: gain: gain: gain: gain: gain: gain: 2.4 1.2 0.6 300 150 75 38 V V V mV mV mV mV
Problem fix/Workaround Keep the amplified voltage output from the ADC gain stage below 2.4 V in order to get a correct result, or keep ADC voltage reference below 2.4 V. 3. Sampled BOD in Active mode will cause noise when bandgap is used as reference Using the BOD in sampled mode when the device is running in Active or Idle mode will add noise on the bandgap reference for ADC, DAC and Analog Comparator. Problem fix/Workaround If the bandgap is used as reference for either the ADC, DAC and Analog Comparator, the BOD must not be set in sampled mode. 4. Bandgap measurement with the ADC is non-functional when VCC is below 2.7V The ADC cannot be used to do bandgap measurements when VCC is below 2.7V. Problem fix/Workaround If internal voltages must be measured when VCC is below 2.7V, measure the internal 1.00V reference instead of the bandgap. 5. BOD will be enabled after any reset If any reset source goes active, the BOD will be enabled and keep the device in reset if the VCC voltage is below the programmed BOD level. During Power-On Reset, reset will not be released until VCC is above the programmed BOD level even if the BOD is disabled. Problem fix/Workaround Do not set the BOD level higher than VCC even if the BOD is not used. 6. Writing EEPROM or Flash while reading any of them will not work The EEPROM and Flash cannot be written while reading EEPROM or Flash, or while executing code in Active mode. Problem fix/Workaround Enter IDLE sleep mode within 2.5 uS (Five 2 MHz clock cycles and 80 32 MHz clock cycles) after starting an EEPROM or flash write operation. Wake-up source must either be EEPROM ready or NVM ready interrupt. Alternatively set up a Timer/Counter to give an
96
8068O-AVR-11/09
XMEGA A3
overflow interrupt 7 mS after the erase or write operation has started, or 13 mS after atomic erase-and-write operation has started, and then enter IDLE sleep mode. 7. ADC has increased INL error for some operating conditions Some ADC configurations or operating condition will result in increased INL error. In differential mode INL is increased to: - 6 LSB for sample rates above 1 Msps, and up to 8 LSB for 2 Msps sample rate. - 6 LSB for reference voltage below 1.1V when VCC is above 3.0V. - 20 LSB for ambient temperature below 0 degree C and reference voltage below 1.3V. In single ended mode, the INL is increased up to a factor of 3 for the conditions above. Problem fix/Workaround None, avoid using the ADC in the above configurations in order to prevent increased INL error. 8. DAC has increased INL or noise for some operating conditions Some DAC configurations or operating condition will result in increased output error. - INL error is increased up to 35 LSB when VCC < 2.0V - Enabling Sample and Hold, will increase noise and reduce resolution below 8 bit Problem fix/Workaround None, avoid using the DAC in the above configurations in order to prevent increased INL error. 9. VCC voltage scaler for AC is non-linear The 6-bit VCC voltage scaler in the Analog Comparators is non-linear. The typical voltage output versus the scale factor for different VCC voltages is shown below: Figure 36-3. Analog Comparator Voltage Scaler vs. Scalefac
T = 25C
3.5 3
3.3 V 2.7 V
2.5 VSCALE [V] 2 1.5 1 0.5 0 0 5 10 15 20 25 30 35 40 45 50 55 60 65 SCALEFAC
1.8 V
97
8068O-AVR-11/09
XMEGA A3
Problem fix/Workaround Use external voltage input for the analog comparator if accurate voltage levels are needed. 10. Maximum operating frequency below 1.76V is 8 MHz To ensure correct operation, the maximum operating frequency below 1.76V VCC is 8 MHz. Problem fix/Workaround None, avoid running the device outside this frequency and voltage limitation.
36.2.2
rev. A Not sampled.
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XMEGA A3
37. Datasheet Revision History
37.1 8068O - 11/09
1. 2. 3.
Updated Table 34-3 on page 64, Endurance and Data Retention. Updated Table 34-11 on page 67, Input hysteresis is in V and not in mV. Updated "Errata" on page 90.
37.2
8068N - 10/09
1.
Updated "Errata" on page 90.
37.3
8068M - 09/09
1. 2. 3.
Updated "Electrical Characteristics" on page 61. Added "Flash and EEPROM Memory Characteristics" on page 64. Added Errata for "ATxmega192A3, ATxmega128A3, ATxmega64A3" on page 95.
37.4
8068L - 06/09
1. 2. 3. 4. 5. 6. 7.
Updated "Ordering Information" on page 2. Updated "Features" on page 39. Updated "Overview" on page 43. Updated "Overview" on page 48. Added "Electrical Characteristics" on page 61. Added "Typical Characteristics" on page 69. Updated ""Errata" on page 90.
37.5
8068K - 02/09
1.
Added "Errata" on page 90 for ATxmega256A3 rev B.
99
8068O-AVR-11/09
XMEGA A3
37.6 8068J - 12/08
1.
Added "Errata" on page 90 for ATxmega256A3 rev A.
37.7
8068I - 11/08
1.
Updated Featurelist in "Memories" on page 9.
37.8
8068H - 10/08
1.
Updated Table 14-1 on page 25.
37.9
8068G - 09/08
1. 2. 3. 4. 5. 6. 7
Updated "Features" on page 1. Updated "Ordering Information" on page 2. Updated "Features" on page 9 by removing "External Memory...". Updated Figure 7-1 on page 10 and Figure 7-2 on page 11. Updated Table 7-2 on page 14 and Table 7-3 on page 14. Updated "Features" on page 41 and "Overview" on page 41. Removed "Interrupt Vector Summary" section from datasheet.
37.10 8068F - 08/08
1. 2. 3. 4.
Changed Figure 2-1's title to "Block diagram and pinout." Changed Package Type to "64M2" in "Ordering Information" on page 2 and in "Errata" on page 90. Updated Table 30-5 on page 52. Inserted a correct "64A" TQFP drawing on page 59.
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8068O-AVR-11/09
XMEGA A3
37.11 8068E - 08/08
1. 2.
Updated "Block Diagram" on page 5. Inserted "Interrupt Vector Summary" on page 54.
37.12 8068D - 06/08
1.
References to External Bus Interface (EBI) removed from "Features" on page 1.
37.13 8068C - 06/08
1. 2. 3. 4. 5. 6. 7.
Updated "Features" on page 1. Updated Figure 2-1 on page 3. Updated "Overview" on page 4. Updated Table 7-2 on page 14. Replaced Figure 25-1 on page 42 by a correct one. Updated "Features" and "Overview" on page 43. Updated all tables in section "Alternate Pin Functions" on page 51.
37.14 8068B - 06/08
1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14.
Updated "Features" on page 1. Updated "" on page 2 and "Pinout and Pin Functions" on page 49. Updated "Ordering Information" on page 2. Updated "Overview" on page 4, included the XMEGA A3 explanation text on page 6. Added XMEGA A3 Block Diagram, Figure 3-1 on page 5. Updated AVR CPU "Overview" on page 7 and Updated Figure 6-1 on page 7. Updated Event System block diagram, Figure 9-1 on page 17. Updated "PMIC - Programmable Multi-level Interrupt Controller" on page 25. Updated "AC - Analog Comparator" on page 44. Updated "I/O configuration" on page 27. Inserted a new Figure 16-1 on page 32. Updated "Peripheral Module Address Map" on page 54. Inserted "Instruction Set Summary" on page 55. Added Speed grades in "Operating Voltage and Frequency" on page 63.
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37.15 8068A - 02/08
1.
Initial revision.
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XMEGA A3
Table of Contents
Features ..................................................................................................... 1 Typical Applications ................................................................................ 1 1 2 3 Ordering Information ............................................................................... 2 Pinout/Block Diagram .............................................................................. 3 Overview ................................................................................................... 4
3.1Block Diagram ...........................................................................................................5
4
Resources ................................................................................................. 6
4.1Recommended reading .............................................................................................6
5 6
Disclaimer ................................................................................................. 6 AVR CPU ................................................................................................... 7
6.1Features ....................................................................................................................7 6.2Overview ...................................................................................................................7 6.3Register File ..............................................................................................................8 6.4ALU - Arithmetic Logic Unit .......................................................................................8 6.5Program Flow ............................................................................................................8
7
Memories .................................................................................................. 9
7.1Features ....................................................................................................................9 7.2Overview ...................................................................................................................9 7.3In-System Programmable Flash Program Memory .................................................10 7.4Data Memory ...........................................................................................................11 7.5Production Signature Row .......................................................................................13 7.6User Signature Row ................................................................................................13 7.7Flash and EEPROM Page Size ...............................................................................14
8
DMAC - Direct Memory Access Controller .......................................... 15
8.1Features ..................................................................................................................15 8.2Overview .................................................................................................................15
9
Event System ......................................................................................... 16
9.1Features ..................................................................................................................16 9.2Overview .................................................................................................................16
10 System Clock and Clock options ......................................................... 18
10.1Features ................................................................................................................18 i
8068N-AVR-10/09
XMEGA A3
10.2Overview ...............................................................................................................18 10.3Clock Options ........................................................................................................19
11 Power Management and Sleep Modes ................................................. 21
11.1Features ................................................................................................................21 11.2Overview ...............................................................................................................21 11.3Sleep Modes .........................................................................................................21
12 System Control and Reset .................................................................... 23
12.1Features ................................................................................................................23 12.2Resetting the AVR .................................................................................................23 12.3Reset Sources .......................................................................................................23
13 WDT - Watchdog Timer ......................................................................... 24
13.1Features ................................................................................................................24 13.2Overview ...............................................................................................................24
14 PMIC - Programmable Multi-level Interrupt Controller ....................... 25
14.1Features ................................................................................................................25 14.2Overview ...............................................................................................................25 14.3Interrupt vectors ....................................................................................................25
15 I/O Ports .................................................................................................. 27
15.1Features ................................................................................................................27 15.2Overview ...............................................................................................................27 15.3I/O configuration ....................................................................................................27 15.4Input sensing .........................................................................................................30 15.5Port Interrupt .........................................................................................................30 15.6Alternate Port Functions ........................................................................................30
16 T/C - 16-bits Timer/Counter with PWM ................................................. 31
16.1Features ................................................................................................................31 16.2Overview ...............................................................................................................31
17 AWEX - Advanced Waveform Extension ............................................. 33
17.1Features ................................................................................................................33 17.2Overview ...............................................................................................................33
18 Hi-Res - High Resolution Extension ..................................................... 34
18.1Features ................................................................................................................34 18.2Overview ...............................................................................................................34
ii
8068N-AVR-10/09
XMEGA A3
19 RTC - Real-Time Counter ...................................................................... 35
19.1Features ................................................................................................................35 19.2Overview ...............................................................................................................35
20 TWI - Two Wire Interface ....................................................................... 36
20.1Features ................................................................................................................36 20.2Overview ...............................................................................................................36
21 SPI - Serial Peripheral Interface ............................................................ 37
21.1Features ................................................................................................................37 21.2Overview ...............................................................................................................37
22 USART ..................................................................................................... 38
22.1Features ................................................................................................................38 22.2Overview ...............................................................................................................38
23 IRCOM - IR Communication Module .................................................... 39
23.1Features ................................................................................................................39 23.2Overview ...............................................................................................................39
24 Crypto Engine ........................................................................................ 40
24.1Features ................................................................................................................40 24.2Overview ...............................................................................................................40
25 ADC - 12-bit Analog to Digital Converter ............................................. 41
25.1Features ................................................................................................................41 25.2Overview ...............................................................................................................41
26 DAC - 12-bit Digital to Analog Converter ............................................. 43
26.1Features ................................................................................................................43 26.2Overview ...............................................................................................................43
27 AC - Analog Comparator ....................................................................... 44
27.1Features ................................................................................................................44 27.2Overview ...............................................................................................................44 27.3Input Selection .......................................................................................................46 27.4Window Function ...................................................................................................46
28 OCD - On-chip Debug ............................................................................ 47
28.1Features ................................................................................................................47 28.2Overview ...............................................................................................................47
29 Program and Debug Interfaces ............................................................. 48
iii
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XMEGA A3
29.1Features ................................................................................................................48 29.2Overview ...............................................................................................................48 29.3JTAG interface ......................................................................................................48 29.4PDI - Program and Debug Interface ......................................................................48
30 Pinout and Pin Functions ...................................................................... 49
30.1Alternate Pin Function Description ........................................................................49 30.2Alternate Pin Functions .........................................................................................51
31 Peripheral Module Address Map .......................................................... 54 32 Instruction Set Summary ...................................................................... 55 33 Packaging information .......................................................................... 59
33.164A ........................................................................................................................59 33.264M2 .....................................................................................................................60
34 Electrical Characteristics ...................................................................... 61
34.1Absolute Maximum Ratings* .................................................................................61 34.2DC Characteristics ................................................................................................61 34.3Operating Voltage and Frequency ........................................................................63 34.4Flash and EEPROM Memory Characteristics .......................................................64 34.5ADC Characteristics ..............................................................................................65 34.6DAC Characteristics ..............................................................................................66 34.7Analog Comparator Characteristics .......................................................................66 34.8Bandgap Characteristics .......................................................................................66 34.9Brownout Detection Characteristics ......................................................................67 34.10PAD Characteristics ............................................................................................67 34.11POR Characteristics ............................................................................................68 34.12Reset Characteristics ..........................................................................................68 34.13Oscillator Characteristics .....................................................................................68
35 Typical Characteristics .......................................................................... 69
35.1Active Supply Current ............................................................................................69 35.2Idle Supply Current ................................................................................................72 35.3Power-down Supply Current .................................................................................76 35.4Power-save Supply Current ..................................................................................77 35.5Pin Pull-up .............................................................................................................77 35.6Pin Output Voltage vs. Sink/Source Current .........................................................79 35.7Pin Thresholds and Hysteresis ..............................................................................82
iv
8068N-AVR-10/09
35.8Bod Thresholds .....................................................................................................84 35.9Internal Oscillator Speed .......................................................................................85 35.10Module current consumption ...............................................................................88 35.11Reset Pulsewidth .................................................................................................89
36 Errata ....................................................................................................... 90
36.1ATxmega256A3 .....................................................................................................90 36.2ATxmega192A3, ATxmega128A3, ATxmega64A3 ...............................................95
37 Datasheet Revision History .................................................................. 99
37.18068O - 11/09 .......................................................................................................99 37.28068N - 10/09 .......................................................................................................99 37.38068M - 09/09 ......................................................................................................99 37.48068L - 06/09 .......................................................................................................99 37.58068K - 02/09 .......................................................................................................99 37.68068J - 12/08 ......................................................................................................100 37.78068I - 11/08 ......................................................................................................100 37.88068H - 10/08 .....................................................................................................100 37.98068G - 09/08 .....................................................................................................100 37.108068F - 08/08 ...................................................................................................100 37.118068E - 08/08 ...................................................................................................101 37.128068D - 06/08 ...................................................................................................101 37.138068C - 06/08 ...................................................................................................101 37.148068B - 06/08 ...................................................................................................101 37.158068A - 02/08 ...................................................................................................102
Table of Contents....................................................................................... i
Headquarters
Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600
International
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